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FMC ADC 100M 14b 4cha
Commit 15094615 authored by Tristan Gingold's avatar Tristan Gingold Committed by Federico Vaga
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spec_sata: fix some issues (still WIP)

parent 50af1a20
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Showing with 10 additions and 6 deletions
hdl/top/spec_sata_design/sata_controller.vhd
View file @ 15094615
......@@ -8,6 +8,8 @@ entity sata_controller is
tx_clk_i : std_logic;
rx_clk_i : std_logic;
rdy_i : in std_logic;
-- TX
reg_tx_data_i : in std_logic_vector(7 downto 0);
reg_tx_wr_i : in std_logic;
......@@ -27,7 +29,7 @@ architecture arch of sata_controller is
signal tx_data_reg : std_logic_vector(7 downto 0);
signal tx_data_wr : std_logic;
signal rx_k_n, rx_wr : std_logic;
signal rx_wr, rx_valid : std_logic;
begin
inst_sync_tx: entity work.gc_sync_word_wr
generic map (
......@@ -50,7 +52,7 @@ begin
tx_data_o <= tx_data_reg when tx_data_wr = '1' else x"bc";
tx_k_o <= not tx_data_wr;
rx_k_n <= not rx_k_i;
rx_valid <= (not rx_k_i) and rdy_i;
inst_rx_data: entity work.gc_sync_word_wr
generic map (
......@@ -63,11 +65,11 @@ begin
clk_out_i => clk_62m5_i,
rst_out_n_i => rst_62m5_n_i,
data_i => rx_data_i,
wr_i => rx_k_n,
wr_i => rx_valid,
busy_o => open,
ack_o => open,
data_o => reg_rx_data_o,
wr_o => open
wr_o => rx_wr
);
process(clk_62m5_i) is
......
hdl/top/spec_sata_design/spec_sata.vhd
View file @ 15094615
......@@ -154,6 +154,7 @@ begin
rst_62m5_n_i => rst_sys_62m5_n_i,
tx_clk_i => clk_ref_125m_i,
rx_clk_i => gtp_rx_clk0,
rdy_i => sata_rdy(0),
reg_tx_data_i => sata_tx_data0(7 downto 0),
reg_tx_wr_i => sata_tx_data_wr(0),
tx_data_o => gtp_tx_data0,
......@@ -209,8 +210,8 @@ begin
ch1_loopen_vec_i => (others => '0'),
ch1_tx_prbs_sel_i => "000",
ch1_rdy_o => open,
ch0_ref_sel_pll => "100",
ch1_ref_sel_pll => "100",
ch0_ref_sel_pll => "000",
ch1_ref_sel_pll => "000",
pad_txn1_o => open,
pad_txp1_o => open,
pad_rxn1_i => '0',
......@@ -227,6 +228,7 @@ begin
rst_62m5_n_i => rst_sys_62m5_n_i,
tx_clk_i => clk_ref_125m_i,
rx_clk_i => gtp_rx_clk0,
rdy_i => sata_rdy(1),
reg_tx_data_i => sata_tx_data1(7 downto 0),
reg_tx_wr_i => sata_tx_data_wr(1),
tx_data_o => gtp_tx_data1,
......
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