sw:drv: fix VME DMA concurrent transfers
On SVEC we can have up to two FMC-ADC-100M mezzanine, potentially
triggering at the same time. If such conditions, the driver fails in
performing the DMA on both mezzanine because one of the two will fail to
request a channel.
With this patch we introducte a 10s timeout for the ADC to request a DMA
channel on SVEC.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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