Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha
Commits
5f61c4fb
Commit
5f61c4fb
authored
Jan 28, 2021
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Revive the testbenches.
parent
09ea6d1b
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
40 additions
and
29 deletions
+40
-29
main.sv
hdl/testbench/fmc_adc_mezzanine/main.sv
+3
-2
main.sv
hdl/testbench/svec_ref_design/main.sv
+34
-24
svec_ref_fmc_adc_100Ms.vhd
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+3
-3
No files found.
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @
5f61c4fb
...
...
@@ -5,14 +5,15 @@
`timescale
1
ns
/
1
ps
`include
"vhd_wishbone_master.svh"
`include
"fmc_adc_mezzanine_mmap.v"
`include
"fmc_adc_100Ms_csr.v"
`include
"timetag_core_regs.v"
`include
"fmc_adc_aux_trigin.v"
`include
"fmc_adc_aux_trigout.v"
`define
SDB_ADDR
'
h0000
`define
CSR_BASE
'
h1000
`define
TAG_BASE
'
h1900
`define
CSR_BASE
`
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define
TAG_BASE
`
ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE
module
main
;
...
...
hdl/testbench/svec_ref_design/main.sv
View file @
5f61c4fb
...
...
@@ -6,14 +6,24 @@
`include
"vme64x_bfm.svh"
`include
"svec_vme_buffers.svh"
`include
"svec_ref_fmc_adc_100Ms_mmap.v"
`include
"fmc_adc_mezzanine_mmap.v"
`include
"fmc_adc_100Ms_csr.v"
`include
"fmc_adc_100Ms_channel_regs.v"
`include
"fmc_adc_eic_regs.v"
`include
"timetag_core_regs.v"
`define
VME_OFFSET
'
h80000000
`define
ADC_OFFSET
'
h4000
`define
ADC1_OFFSET
`
VME_OFFSET
+
`
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE
`define
ADC2_OFFSET
`
VME_OFFSET
+
`
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE
`define
CSR_BASE
`
VME_OFFSET
+
`
ADC_OFFSET
+
'
h1000
`define
OWC_BASE
`
VME_OFFSET
+
`
ADC_OFFSET
+
'
h1700
`define
TAG_BASE
`
VME_OFFSET
+
`
ADC_OFFSET
+
'
h1900
`define
CSR_BASE
`
ADC1_OFFSET
+
`
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define
CH1_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1
`define
CH2_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2
`define
CH3_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3
`define
CH4_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4
`define
EIC_BASE
`
ADC1_OFFSET
+
`
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC
`define
TAG_BASE
`
ADC1_OFFSET
+
`
ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE
module
main
;
...
...
@@ -255,14 +265,13 @@ module main;
/* map func0 to 0x80000000, A32 */
acc
.
write
(
'h7ff63
,
'h80
,
A32
|
CR_CSR
|
D08Byte3
)
;
acc
.
write
(
'h7ff67
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6b
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6f
,
36
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff33
,
1
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff63
,
'h80
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff67
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6b
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6f
,
36
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff33
,
1
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7fffb
,
'h10
,
CR_CSR
|
A32
|
D08Byte3
)
;
/* enable module (BIT_SET = 0x10) */
acc
.
set_default_modifiers
(
A32
|
D32
|
SINGLE
)
;
endtask
// init_vme64x_core
...
...
@@ -309,22 +318,23 @@ module main;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h00000001
)
;
// FMC-ADC core channel configuration
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH1_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH2_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH3_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH4_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH1_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH2_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH3_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH4_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CTL
,
`FMC_ADC_100MS_CSR_CTL_CALIB_APPLY
)
;
// FMC-ADC core trigger configuration
val
=
(
16'h100
<<
`FMC_ADC_100MS_C
SR_CH1
_TRIG_THRES_HYST_OFFSET
)
|
(
16'h300
<<
`FMC_ADC_100MS_C
SR_CH1
_TRIG_THRES_VAL_OFFSET
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4
_TRIG_THRES
,
val
)
;
val
=
(
16'h100
<<
`FMC_ADC_100MS_C
HANNEL_REGS
_TRIG_THRES_HYST_OFFSET
)
|
(
16'h300
<<
`FMC_ADC_100MS_C
HANNEL_REGS
_TRIG_THRES_VAL_OFFSET
)
;
acc
.
write
(
`C
H1_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
H2_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
H3_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
H4_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
val
=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_EN
,
val
)
;
...
...
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @
5f61c4fb
...
...
@@ -503,9 +503,9 @@ begin -- architecture arch
gen_fmc_mezzanine
:
for
I
in
0
to
g_NB_FMC_SLOTS
-
1
generate
cmp_xwb_clock_bridge
:
xwb_clock_bridge
generic
map
(
g_SLAVE_PORT_WB_MODE
=>
CLASSIC
,
g_MASTER_PORT_WB_MODE
=>
PIPELINED
)
generic
map
(
g_SLAVE_PORT_WB_MODE
=>
CLASSIC
,
g_MASTER_PORT_WB_MODE
=>
PIPELINED
)
port
map
(
slave_clk_i
=>
clk_sys_62m5
,
slave_rst_n_i
=>
rst_sys_62m5_n
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment