Skip to content

F
FMC ADC 100M 14b 4cha
Commit 09ea6d1b authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

hdl: add a skidpad to relax timing constraints to ddr.

parent 96563b44
Hide whitespace changes
Inline Side-by-side
Showing with 42 additions and 11 deletions
general-cores @ 67100ef6
Subproject commit 347e0de1e0d91834d298a146569530b71adeb33a
Subproject commit 67100ef69d1d65cbb33f80475f860de996bdf619
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 09ea6d1b
......@@ -299,6 +299,12 @@ architecture rtl of fmc_adc_100Ms_core is
signal wb_ddr_fifo_rd : std_logic;
signal wb_ddr_fifo_wr_en : std_logic;
signal wb_ddr_skidpad_stb_in : std_logic;
signal wb_ddr_skidpad_stb_out : std_logic;
signal wb_ddr_skidpad_stall : std_logic;
signal wb_ddr_skidpad_adr_in : std_logic_vector(28 downto 0);
signal wb_ddr_skidpad_adr_out : std_logic_vector(28 downto 0);
-- RAM address counter
signal ram_addr_cnt : unsigned(28 downto 0);
signal trig_addr : std_logic_vector(31 downto 0);
......@@ -1599,7 +1605,7 @@ begin
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_master_i.stall);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_skidpad_stall);
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
......@@ -1614,20 +1620,45 @@ begin
else
if acq_start = '1' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_empty = '0' and wb_ddr_master_i.stall = '0' then
elsif wb_ddr_fifo_empty = '0' and wb_ddr_skidpad_stall = '0' then
ram_addr_cnt <= ram_addr_cnt + 1;
end if;
end if;
end if;
end process p_ram_addr_cnt;
wb_ddr_master_o.cyc <= dpram_valid or not wb_ddr_fifo_empty when acq_fsm_state = "001" else '1';
wb_ddr_master_o.stb <= not wb_ddr_fifo_empty;
wb_ddr_skidpad_stb_in <= not wb_ddr_fifo_empty;
-- Convert to 32-bit word addressing for Wishbone
wb_ddr_master_o.adr <= "00" & std_logic_vector(ram_addr_cnt) & "0";
wb_ddr_skidpad_adr_in <= std_logic_vector(ram_addr_cnt);
inst_skidpad: entity work.wb_skidpad2
generic map (
g_adrbits => ram_addr_cnt'length,
g_datbits => 64
)
port map (
clk_i => wb_ddr_clk_i,
rst_n_i => wb_ddr_rst_n_i,
stb_i => wb_ddr_skidpad_stb_in,
adr_i => wb_ddr_skidpad_adr_in,
dat_i => wb_ddr_fifo_dout(63 downto 0),
sel_i => (others => '1'),
we_i => '1',
stall_o => wb_ddr_skidpad_stall,
stb_o => wb_ddr_skidpad_stb_out,
adr_o => wb_ddr_skidpad_adr_out,
dat_o => wb_ddr_master_o.dat,
sel_o => open,
we_o => open,
stall_i => wb_ddr_master_i.stall
);
wb_ddr_master_o.we <= '1';
wb_ddr_master_o.sel <= X"FF";
wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
wb_ddr_master_o.cyc <= dpram_valid or wb_ddr_skidpad_stb_out when acq_fsm_state = "001" else '1';
wb_ddr_master_o.stb <= wb_ddr_skidpad_stb_out;
wb_ddr_master_o.adr <= "00" & wb_ddr_skidpad_adr_out & "0";
-- Store trigger DDR address (byte address)
p_trig_addr : process (wb_ddr_clk_i)
......
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @ 09ea6d1b
......@@ -203,14 +203,14 @@ NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
#TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
#TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 8ns DATAPATHONLY;
# No sync words used in FMC-ADC
#TIMESPEC TS_adc0_sync_word = FROM sync_word TO fs0_clk 30ns DATAPATHONLY;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment