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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
59d9f89c
Commit
59d9f89c
authored
Nov 12, 2020
by
Dimitris Lampridis
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hdl: fix wrong handling of cheby 'wire' bits
Signed-off-by:
Dimitris Lampridis
<
dimitris.lampridis@cern.ch
>
parent
ca60307b
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2 changed files
with
46 additions
and
21 deletions
+46
-21
fmc_adc_100Ms_core.vhd
hdl/rtl/fmc_adc_100Ms_core.vhd
+25
-6
main.sv
hdl/testbench/spec_ref_design/main.sv
+21
-15
No files found.
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @
59d9f89c
...
...
@@ -492,6 +492,11 @@ begin
fmc_adc_ch4_i
=>
wb_channel_out
(
4
),
fmc_adc_ch4_o
=>
wb_channel_in
(
4
));
csr_regin
.
ctl_fsm_cmd
<=
fsm_cmd
;
csr_regin
.
ctl_man_bitslip
<=
serdes_man_bitslip
;
csr_regin
.
ctl_clear_trig_stat
<=
trig_storage_clear
;
csr_regin
.
ctl_calib_apply
<=
sync_calib_apply
;
csr_regin
.
sta_fsm
<=
acq_fsm_state
;
csr_regin
.
sta_serdes_pll
<=
serdes_locked_sync
;
csr_regin
.
sta_serdes_synced
<=
serdes_synced_sync
;
...
...
@@ -514,12 +519,8 @@ begin
csr_regin
.
multi_depth
<=
c_MULTISHOT_SAMPLE_DEPTH
;
ctl_reg_wr
<=
csr_regout
.
ctl_wr
;
fsm_cmd
<=
csr_regout
.
ctl_fsm_cmd
;
serdes_man_bitslip
<=
csr_regout
.
ctl_man_bitslip
and
ctl_reg_wr
;
trig_led_man
<=
csr_regout
.
ctl_trig_led
;
acq_led_man
<=
csr_regout
.
ctl_acq_led
;
trig_storage_clear
<=
csr_regout
.
ctl_clear_trig_stat
and
ctl_reg_wr
;
sync_calib_apply
<=
csr_regout
.
ctl_calib_apply
and
ctl_reg_wr
;
int_trig_en_in
(
1
)
<=
csr_regout
.
trig_en_ch1
;
int_trig_en_in
(
2
)
<=
csr_regout
.
trig_en_ch2
;
int_trig_en_in
(
3
)
<=
csr_regout
.
trig_en_ch3
;
...
...
@@ -532,6 +533,24 @@ begin
pre_trig_value
<=
csr_regout
.
pre_samples
;
post_trig_value
<=
csr_regout
.
post_samples
;
-- external register for "wire" bits of the control register
p_ext_reg_ctl
:
process
(
sys_clk_i
)
is
begin
if
rising_edge
(
sys_clk_i
)
then
if
ctl_reg_wr
=
'1'
then
fsm_cmd
<=
csr_regout
.
ctl_fsm_cmd
;
serdes_man_bitslip
<=
csr_regout
.
ctl_man_bitslip
;
trig_storage_clear
<=
csr_regout
.
ctl_clear_trig_stat
;
sync_calib_apply
<=
csr_regout
.
ctl_calib_apply
;
else
fsm_cmd
<=
(
others
=>
'0'
);
serdes_man_bitslip
<=
'0'
;
trig_storage_clear
<=
'0'
;
sync_calib_apply
<=
'0'
;
end
if
;
end
if
;
end
process
p_ext_reg_ctl
;
-- Delays for user-controlled GPIO outputs to help with timing
p_delay_gpio_ssr
:
process
(
sys_clk_i
)
is
begin
...
...
@@ -1166,8 +1185,8 @@ begin
acq_end_p_o
<=
acq_end
and
not
(
acq_end_d
);
-- FSM commands
acq_start
<=
'1'
when
ctl_reg_wr
=
'1'
and
fsm_cmd
=
"01"
else
'0'
;
acq_stop
<=
'1'
when
ctl_reg_wr
=
'1'
and
fsm_cmd
=
"10"
else
'0'
;
acq_start
<=
'1'
when
fsm_cmd
=
"01"
else
'0'
;
acq_stop
<=
'1'
when
fsm_cmd
=
"10"
else
'0'
;
acq_trig
<=
sync_fifo_valid
and
sync_fifo_dout
(
64
)
and
acq_in_wait_trig
;
acq_end
<=
trig_tag_done
and
shots_done
;
...
...
hdl/testbench/spec_ref_design/main.sv
View file @
59d9f89c
...
...
@@ -4,6 +4,7 @@
`include
"spec_ref_fmc_adc_100Ms_mmap.v"
`include
"fmc_adc_mezzanine_mmap.v"
`include
"fmc_adc_100Ms_csr.v"
`include
"fmc_adc_100Ms_channel_regs.v"
`include
"fmc_adc_eic_regs.v"
`include
"timetag_core_regs.v"
...
...
@@ -12,6 +13,10 @@
`define
ADC_OFFSET
`
ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE
`define
CSR_BASE
`
ADC_OFFSET
+
`
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define
CH1_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1
`define
CH2_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2
`define
CH3_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3
`define
CH4_BASE
`
CSR_BASE
+
`
ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4
`define
EIC_BASE
`
ADC_OFFSET
+
`
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC
`define
TAG_BASE
`
ADC_OFFSET
+
`
ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE
...
...
@@ -242,23 +247,24 @@ module main;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h00000001
)
;
// FMC-ADC core channel configuration
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_CALIB
,
'h00008000
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CTL
,
'h00008000
)
;
// apply calibration
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH1_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH2_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH3_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH4_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB
,
'h00008000
)
;
acc
.
write
(
`CH1_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH2_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH3_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CH4_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT
,
'h00007fff
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CTL
,
`FMC_ADC_100MS_CSR_CTL_CALIB_APPLY
)
;
// FMC-ADC core trigger configuration
val
=
(
16'h100
<<
`FMC_ADC_100MS_C
SR_CH1
_TRIG_THRES_HYST_OFFSET
)
|
(
16'h300
<<
`FMC_ADC_100MS_C
SR_CH1
_TRIG_THRES_VAL_OFFSET
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
SR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4
_TRIG_THRES
,
val
)
;
val
=
(
16'h100
<<
`FMC_ADC_100MS_C
HANNEL_REGS
_TRIG_THRES_HYST_OFFSET
)
|
(
16'h300
<<
`FMC_ADC_100MS_C
HANNEL_REGS
_TRIG_THRES_VAL_OFFSET
)
;
acc
.
write
(
`C
H1_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
H2_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
H3_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
acc
.
write
(
`C
H4_BASE
+
`ADDR_FMC_ADC_100MS_CHANNEL_REGS
_TRIG_THRES
,
val
)
;
val
=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_EN
,
val
)
;
...
...
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