hdl/testbench/spec_ref_design/main.sv · 59d9f89cf0b8c444b6df4555dc508e7df70374fb · Projects / FMC ADC 100M 14b 4cha · Open Hardware Repository

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hdl: fix wrong handling of cheby 'wire' bits · 59d9f89c
Dimitris Lampridis authored Nov 12, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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59d9f89c

main.sv 14.3 KB