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FMC ADC 100M 14b 4cha
Commits
3501364d
Commit
3501364d
authored
Jul 31, 2019
by
Dimitris Lampridis
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Migrate Timetag Core to Cheby
parent
e084c507
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21 changed files
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2033 additions
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7167 deletions
+2033
-7167
timetag_core_regs.adoc
doc/manual/timetag_core_regs.adoc
+1292
-0
Manifest.py
hdl/rtl/Manifest.py
+2
-6
fmc_adc_100Ms_core.vhd
hdl/rtl/fmc_adc_100Ms_core.vhd
+1
-1
fmc_adc_100Ms_core_pkg.vhd
hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
+1
-1
fmc_adc_mezzanine.vhd
hdl/rtl/fmc_adc_mezzanine.vhd
+7
-17
fmc_adc_mezzanine_pkg.vhd
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
+1
-1
timetag_core.vhd
hdl/rtl/timetag_core.vhd
+82
-84
Manifest.py
hdl/rtl/timetag_core/Manifest.py
+0
-6
timetag_core_pkg.vhd
hdl/rtl/timetag_core/timetag_core_pkg.vhd
+0
-54
timetag_core_regs.vhd
hdl/rtl/timetag_core/timetag_core_regs.vhd
+0
-407
timetag_core_regs_wbgen2_pkg.vhd
hdl/rtl/timetag_core/timetag_core_regs_wbgen2_pkg.vhd
+0
-129
Makefile
hdl/rtl/timetag_core/wb_gen/Makefile
+0
-8
timetag_core_regs.h
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.h
+0
-113
timetag_core_regs.htm
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.htm
+0
-6050
timetag_core_regs.wb
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.wb
+0
-263
timetag_core_regs.cheby
hdl/rtl/timetag_core_regs.cheby
+227
-0
timetag_core_regs.vhd
hdl/rtl/timetag_core_regs.vhd
+370
-0
main.sv
hdl/testbench/fmc_adc_mezzanine/main.sv
+7
-7
timetag_core_regs.v
hdl/testbench/include/timetag_core_regs.v
+43
-18
spec_ref_fmc_adc_100Ms.vhd
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+0
-1
svec_ref_fmc_adc_100Ms.vhd
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+0
-1
No files found.
doc/manual/timetag_core_regs.adoc
0 → 100644
View file @
3501364d
== Memory map summary
Time-tagging core registers
|===
|HW address | Type | Name | HDL name
|0x00
|REG
|seconds_upper
|seconds_upper
|0x04
|REG
|seconds_lower
|seconds_lower
|0x08
|REG
|coarse
|coarse
|0x0c
|REG
|time_trig_seconds_upper
|time_trig_seconds_upper
|0x10
|REG
|time_trig_seconds_lower
|time_trig_seconds_lower
|0x14
|REG
|time_trig_coarse
|time_trig_coarse
|0x18
|REG
|trig_tag_seconds_upper
|trig_tag_seconds_upper
|0x1c
|REG
|trig_tag_seconds_lower
|trig_tag_seconds_lower
|0x20
|REG
|trig_tag_coarse
|trig_tag_coarse
|0x24
|REG
|acq_start_tag_seconds_upper
|acq_start_tag_seconds_upper
|0x28
|REG
|acq_start_tag_seconds_lower
|acq_start_tag_seconds_lower
|0x2c
|REG
|acq_start_tag_coarse
|acq_start_tag_coarse
|0x30
|REG
|acq_stop_tag_seconds_upper
|acq_stop_tag_seconds_upper
|0x34
|REG
|acq_stop_tag_seconds_lower
|acq_stop_tag_seconds_lower
|0x38
|REG
|acq_stop_tag_coarse
|acq_stop_tag_coarse
|0x3c
|REG
|acq_end_tag_seconds_upper
|acq_end_tag_seconds_upper
|0x40
|REG
|acq_end_tag_seconds_lower
|acq_end_tag_seconds_lower
|0x44
|REG
|acq_end_tag_coarse
|acq_end_tag_coarse
|===
== Registers description
=== seconds_upper
[horizontal]
HDL name:: seconds_upper
address:: 0x0
block offset:: 0x0
access mode:: rw
Timetag seconds register (upper)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| seconds_upper[7:0]
|===
:: Timetag seconds
=== seconds_lower
[horizontal]
HDL name:: seconds_lower
address:: 0x4
block offset:: 0x4
access mode:: rw
Timetag seconds register (lower)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| seconds_lower[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| seconds_lower[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| seconds_lower[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| seconds_lower[7:0]
|===
=== coarse
[horizontal]
HDL name:: coarse
address:: 0x8
block offset:: 0x8
access mode:: rw
Timetag coarse time register, system clock ticks (125MHz)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| coarse[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| coarse[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| coarse[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| coarse[7:0]
|===
:: Timetag coarse time
=== time_trig_seconds_upper
[horizontal]
HDL name:: time_trig_seconds_upper
address:: 0xc
block offset:: 0xc
access mode:: rw
Time trigger seconds register (upper)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| time_trig_seconds_upper[7:0]
|===
:: Time trigger seconds
=== time_trig_seconds_lower
[horizontal]
HDL name:: time_trig_seconds_lower
address:: 0x10
block offset:: 0x10
access mode:: rw
Time trigger seconds register (lower)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| time_trig_seconds_lower[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| time_trig_seconds_lower[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| time_trig_seconds_lower[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| time_trig_seconds_lower[7:0]
|===
=== time_trig_coarse
[horizontal]
HDL name:: time_trig_coarse
address:: 0x14
block offset:: 0x14
access mode:: rw
Time trigger coarse time register, system clock ticks (125MHz)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| time_trig_coarse[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| time_trig_coarse[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| time_trig_coarse[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| time_trig_coarse[7:0]
|===
:: Time trigger coarse value
=== trig_tag_seconds_upper
[horizontal]
HDL name:: trig_tag_seconds_upper
address:: 0x18
block offset:: 0x18
access mode:: ro
Trigger time-tag seconds register (upper)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| trig_tag_seconds_upper[7:0]
|===
:: Holds time-tag seconds of the last trigger event
=== trig_tag_seconds_lower
[horizontal]
HDL name:: trig_tag_seconds_lower
address:: 0x1c
block offset:: 0x1c
access mode:: ro
Trigger time-tag seconds register (lower)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| trig_tag_seconds_lower[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| trig_tag_seconds_lower[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| trig_tag_seconds_lower[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| trig_tag_seconds_lower[7:0]
|===
=== trig_tag_coarse
[horizontal]
HDL name:: trig_tag_coarse
address:: 0x20
block offset:: 0x20
access mode:: ro
Trigger time-tag coarse time (system clock ticks 125MHz) register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| trig_tag_coarse[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| trig_tag_coarse[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| trig_tag_coarse[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| trig_tag_coarse[7:0]
|===
:: Holds time-tag coarse time of the last trigger event
=== acq_start_tag_seconds_upper
[horizontal]
HDL name:: acq_start_tag_seconds_upper
address:: 0x24
block offset:: 0x24
access mode:: ro
Acquisition start time-tag seconds register (upper)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_start_tag_seconds_upper[7:0]
|===
:: Holds time-tag seconds of the last acquisition start event
=== acq_start_tag_seconds_lower
[horizontal]
HDL name:: acq_start_tag_seconds_lower
address:: 0x28
block offset:: 0x28
access mode:: ro
Acquisition start time-tag seconds register (lower)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| acq_start_tag_seconds_lower[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| acq_start_tag_seconds_lower[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| acq_start_tag_seconds_lower[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_start_tag_seconds_lower[7:0]
|===
=== acq_start_tag_coarse
[horizontal]
HDL name:: acq_start_tag_coarse
address:: 0x2c
block offset:: 0x2c
access mode:: ro
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| acq_start_tag_coarse[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| acq_start_tag_coarse[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| acq_start_tag_coarse[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_start_tag_coarse[7:0]
|===
:: Holds time-tag coarse time of the last acquisition start event
=== acq_stop_tag_seconds_upper
[horizontal]
HDL name:: acq_stop_tag_seconds_upper
address:: 0x30
block offset:: 0x30
access mode:: ro
Acquisition stop time-tag seconds register (upper)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_stop_tag_seconds_upper[7:0]
|===
:: Holds time-tag seconds of the last acquisition stop event
=== acq_stop_tag_seconds_lower
[horizontal]
HDL name:: acq_stop_tag_seconds_lower
address:: 0x34
block offset:: 0x34
access mode:: ro
Acquisition stop time-tag seconds register (lower)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| acq_stop_tag_seconds_lower[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| acq_stop_tag_seconds_lower[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| acq_stop_tag_seconds_lower[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_stop_tag_seconds_lower[7:0]
|===
=== acq_stop_tag_coarse
[horizontal]
HDL name:: acq_stop_tag_coarse
address:: 0x38
block offset:: 0x38
access mode:: ro
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| acq_stop_tag_coarse[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| acq_stop_tag_coarse[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| acq_stop_tag_coarse[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_stop_tag_coarse[7:0]
|===
:: Holds time-tag coarse time of the last acquisition stop event
=== acq_end_tag_seconds_upper
[horizontal]
HDL name:: acq_end_tag_seconds_upper
address:: 0x3c
block offset:: 0x3c
access mode:: ro
Acquisition end time-tag seconds register (upper)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_end_tag_seconds_upper[7:0]
|===
:: Holds time-tag seconds of the last acquisition end event
=== acq_end_tag_seconds_lower
[horizontal]
HDL name:: acq_end_tag_seconds_lower
address:: 0x40
block offset:: 0x40
access mode:: ro
Acquisition end time-tag seconds register (lower)
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| acq_end_tag_seconds_lower[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| acq_end_tag_seconds_lower[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| acq_end_tag_seconds_lower[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_end_tag_seconds_lower[7:0]
|===
=== acq_end_tag_coarse
[horizontal]
HDL name:: acq_end_tag_coarse
address:: 0x44
block offset:: 0x44
access mode:: ro
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| acq_end_tag_coarse[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| acq_end_tag_coarse[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| acq_end_tag_coarse[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| acq_end_tag_coarse[7:0]
|===
:: Holds time-tag coarse time of the last acquisition end event
hdl/rtl/Manifest.py
View file @
3501364d
...
...
@@ -8,10 +8,6 @@ files = [
"fmc_adc_alt_trigout.vhd"
,
"fmc_adc_eic.vhd"
,
"offset_gain_s.vhd"
,
"timetag_core_regs.vhd"
,
"timetag_core.vhd"
,
]
modules
=
{
"local"
:
[
"timetag_core"
,
],
}
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @
3501364d
...
...
@@ -33,7 +33,7 @@ library unisim;
use
unisim
.
vcomponents
.
all
;
library
work
;
use
work
.
timetag_core_pkg
.
all
;
use
work
.
timetag_core_
defs_
pkg
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
...
...
hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @
3501364d
...
...
@@ -35,7 +35,7 @@
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
use
work
.
timetag_core_pkg
.
all
;
use
work
.
timetag_core_
defs_
pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
fmc_adc_100Ms_core_pkg
is
...
...
hdl/rtl/fmc_adc_mezzanine.vhd
View file @
3501364d
...
...
@@ -34,8 +34,8 @@ use IEEE.NUMERIC_STD.all;
library
work
;
use
work
.
fmc_adc_100Ms_core_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
timetag_core_pkg
.
all
;
use
work
.
timetag_core_
regs_
pkg
.
all
;
use
work
.
timetag_core_defs_pkg
.
all
;
entity
fmc_adc_mezzanine
is
generic
(
...
...
@@ -592,6 +592,8 @@ begin
------------------------------------------------------------------------------
cmp_timetag_core
:
entity
work
.
timetag_core
generic
map
(
g_WB_MODE
=>
PIPELINED
,
g_WB_GRANULARITY
=>
BYTE
,
-- Systematic delay introduced to the time tag by the FMC-ADC-100M core.
-- Measured experimentally.
g_TAG_ADJUST
=>
g_TAG_ADJUST
)
...
...
@@ -619,15 +621,8 @@ begin
alt_trigin_tag_i
=>
alt_trigin_tag
,
alt_trigin_o
=>
alt_time_trigger
,
wb_adr_i
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
)
.
adr
(
6
downto
2
),
-- cnx_slave_in.adr is byte address
wb_dat_i
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
)
.
dat
,
wb_dat_o
=>
cnx_slave_out
(
c_WB_SLAVE_TIMETAG
)
.
dat
,
wb_cyc_i
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
)
.
cyc
,
wb_sel_i
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
)
.
sel
,
wb_stb_i
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
)
.
stb
,
wb_we_i
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
)
.
we
,
wb_ack_o
=>
cnx_slave_out
(
c_WB_SLAVE_TIMETAG
)
.
ack
);
wb_i
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
),
wb_o
=>
cnx_slave_out
(
c_WB_SLAVE_TIMETAG
));
cmp_alt_trigin
:
entity
work
.
alt_trigin
port
map
(
...
...
@@ -647,9 +642,4 @@ begin
alt_trigin_tag
<=
(
seconds
=>
alt_trigin_secs
(
39
downto
0
),
coarse
=>
alt_trigin_cycs
(
27
downto
0
));
-- Unused wishbone signals
cnx_slave_out
(
c_WB_SLAVE_TIMETAG
)
.
err
<=
'0'
;
cnx_slave_out
(
c_WB_SLAVE_TIMETAG
)
.
rty
<=
'0'
;
cnx_slave_out
(
c_WB_SLAVE_TIMETAG
)
.
stall
<=
'0'
;
end
rtl
;
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @
3501364d
...
...
@@ -34,7 +34,7 @@
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
use
work
.
timetag_core_pkg
.
all
;
use
work
.
timetag_core_
defs_
pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
fmc_adc_mezzanine_pkg
is
...
...
hdl/rtl/timetag_core
/timetag_core
.vhd
→
hdl/rtl/timetag_core.vhd
View file @
3501364d
...
...
@@ -4,8 +4,6 @@
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : timetag_core.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-11-18
-- Standard : VHDL'93/02
...
...
@@ -27,19 +25,35 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2011-11-18 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
use
work
.
timetag_core_pkg
.
all
;
use
work
.
timetag_core_wbgen2_pkg
.
all
;
package
timetag_core_defs_pkg
is
type
t_timetag
is
record
seconds
:
std_logic_vector
(
39
downto
0
);
coarse
:
std_logic_vector
(
27
downto
0
);
end
record
t_timetag
;
constant
c_TAG_COARSE_MAX
:
unsigned
:
=
to_unsigned
(
125000000
,
28
);
end
timetag_core_defs_pkg
;
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
timetag_core_regs_pkg
.
all
;
use
work
.
timetag_core_defs_pkg
.
all
;
entity
timetag_core
is
generic
(
-- WB interface configuration
g_WB_MODE
:
t_wishbone_interface_mode
:
=
PIPELINED
;
g_WB_GRANULARITY
:
t_wishbone_address_granularity
:
=
BYTE
;
-- Value to be subtracted from trigger tag coarse counter.
-- This is useful if you know that the system introduces
-- some systematic delay wrt the actual trigger time
...
...
@@ -75,41 +89,12 @@ entity timetag_core is
alt_trigin_o
:
out
std_logic
;
-- Wishbone interface
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
);
end
timetag_core
;
architecture
rtl
of
timetag_core
is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component
timetag_core_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_timetag_core_in_registers
;
regs_o
:
out
t_timetag_core_out_registers
);
end
component
timetag_core_regs
;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
...
...
@@ -128,13 +113,16 @@ architecture rtl of timetag_core is
signal
wr_enabled
:
std_logic
:
=
'0'
;
signal
regin
:
t_timetag_core_
in_registers
;
signal
regout
:
t_timetag_core_
out_registers
;
signal
regin
:
t_timetag_core_
master_in
;
signal
regout
:
t_timetag_core_
master_out
;
signal
alt_trigin
:
std_logic
;
signal
alt_trigin_d
:
std_logic
;
signal
alt_trigin_enable
:
std_logic
;
signal
wb_in
:
t_wishbone_slave_in
;
signal
wb_out
:
t_wishbone_slave_out
;
begin
-- logic to detect if WR is enabled and timecode is valid
...
...
@@ -143,40 +131,50 @@ begin
------------------------------------------------------------------------------
-- Wishbone interface to UTC core registers
------------------------------------------------------------------------------
cmp_timetag_core_regs
:
timetag_core_regs
cmp_timetag_wb_slave_adapter_in
:
wb_slave_adapter
generic
map
(
g_master_use_struct
=>
TRUE
,
g_master_mode
=>
PIPELINED
,
g_master_granularity
=>
BYTE
,
g_slave_use_struct
=>
TRUE
,
g_slave_mode
=>
g_WB_MODE
,
g_slave_granularity
=>
g_WB_GRANULARITY
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_i
,
wb_adr_i
=>
wb_adr_i
,
wb_dat_i
=>
wb_dat_i
,
wb_dat_o
=>
wb_dat_o
,
wb_cyc_i
=>
wb_cyc_i
,
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stb_i
,
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_ack_o
,
wb_stall_o
=>
open
,
regs_i
=>
regin
,
regs_o
=>
regout
);
regin
.
seconds_upper_i
<=
current_time
.
seconds
(
39
downto
32
);
regin
.
seconds_lower_i
<=
current_time
.
seconds
(
31
downto
0
);
regin
.
coarse_i
<=
current_time
.
coarse
;
regin
.
trig_tag_seconds_upper_i
<=
trig_tag
.
seconds
(
39
downto
32
);
regin
.
trig_tag_seconds_lower_i
<=
trig_tag
.
seconds
(
31
downto
0
);
regin
.
trig_tag_coarse_i
<=
trig_tag
.
coarse
;
regin
.
acq_start_tag_seconds_upper_i
<=
acq_start_tag
.
seconds
(
39
downto
32
);
regin
.
acq_start_tag_seconds_lower_i
<=
acq_start_tag
.
seconds
(
31
downto
0
);
regin
.
acq_start_tag_coarse_i
<=
acq_start_tag
.
coarse
;
regin
.
acq_stop_tag_seconds_upper_i
<=
acq_stop_tag
.
seconds
(
39
downto
32
);
regin
.
acq_stop_tag_seconds_lower_i
<=
acq_stop_tag
.
seconds
(
31
downto
0
);
regin
.
acq_stop_tag_coarse_i
<=
acq_stop_tag
.
coarse
;
regin
.
acq_end_tag_seconds_upper_i
<=
acq_end_tag
.
seconds
(
39
downto
32
);
regin
.
acq_end_tag_seconds_lower_i
<=
acq_end_tag
.
seconds
(
31
downto
0
);
regin
.
acq_end_tag_coarse_i
<=
acq_end_tag
.
coarse
;
time_trigger
.
seconds
<=
regout
.
time_trig_seconds_upper_o
&
regout
.
time_trig_seconds_lower_o
;
time_trigger
.
coarse
<=
regout
.
time_trig_coarse_o
;
rst_n_i
=>
rst_n_i
,
slave_i
=>
wb_i
,
slave_o
=>
wb_o
,
master_i
=>
wb_out
,
master_o
=>
wb_in
);
cmp_timetag_core_regs
:
entity
work
.
timetag_core_regs
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_i
,
wb_i
=>
wb_in
,
wb_o
=>
wb_out
,
timetag_core_i
=>
regin
,
timetag_core_o
=>
regout
);
regin
.
seconds_upper
<=
current_time
.
seconds
(
39
downto
32
);
regin
.
seconds_lower
<=
current_time
.
seconds
(
31
downto
0
);
regin
.
coarse
<=
current_time
.
coarse
;
regin
.
trig_tag_seconds_upper
<=
trig_tag
.
seconds
(
39
downto
32
);
regin
.
trig_tag_seconds_lower
<=
trig_tag
.
seconds
(
31
downto
0
);
regin
.
trig_tag_coarse
<=
trig_tag
.
coarse
;
regin
.
acq_start_tag_seconds_upper
<=
acq_start_tag
.
seconds
(
39
downto
32
);
regin
.
acq_start_tag_seconds_lower
<=
acq_start_tag
.
seconds
(
31
downto
0
);
regin
.
acq_start_tag_coarse
<=
acq_start_tag
.
coarse
;
regin
.
acq_stop_tag_seconds_upper
<=
acq_stop_tag
.
seconds
(
39
downto
32
);
regin
.
acq_stop_tag_seconds_lower
<=
acq_stop_tag
.
seconds
(
31
downto
0
);
regin
.
acq_stop_tag_coarse
<=
acq_stop_tag
.
coarse
;
regin
.
acq_end_tag_seconds_upper
<=
acq_end_tag
.
seconds
(
39
downto
32
);
regin
.
acq_end_tag_seconds_lower
<=
acq_end_tag
.
seconds
(
31
downto
0
);
regin
.
acq_end_tag_coarse
<=
acq_end_tag
.
coarse
;
time_trigger
.
seconds
<=
regout
.
time_trig_seconds_upper
&
regout
.
time_trig_seconds_lower
;
time_trigger
.
coarse
<=
regout
.
time_trig_coarse
;
------------------------------------------------------------------------------
-- UTC seconds counter
...
...
@@ -186,10 +184,10 @@ begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
time_counter
.
seconds
<=
(
others
=>
'0'
);
elsif
regout
.
seconds_upper_
load_o
=
'1'
then
time_counter
.
seconds
(
39
downto
32
)
<=
regout
.
seconds_upper
_o
;
elsif
regout
.
seconds_lower_
load_o
=
'1'
then
time_counter
.
seconds
(
31
downto
0
)
<=
regout
.
seconds_lower
_o
;
elsif
regout
.
seconds_upper_
wr
=
'1'
then
time_counter
.
seconds
(
39
downto
32
)
<=
regout
.
seconds_upper
;
elsif
regout
.
seconds_lower_
wr
=
'1'
then
time_counter
.
seconds
(
31
downto
0
)
<=
regout
.
seconds_lower
;
elsif
local_pps
=
'1'
then
time_counter
.
seconds
<=
std_logic_vector
(
unsigned
(
current_time
.
seconds
)
+
1
);
else
...
...
@@ -209,8 +207,8 @@ begin
if
rst_n_i
=
'0'
then
time_counter
.
coarse
<=
(
others
=>
'0'
);
local_pps
<=
'0'
;
elsif
regout
.
coarse_
load_o
=
'1'
then
time_counter
.
coarse
<=
regout
.
coarse
_o
;
elsif
regout
.
coarse_
wr
=
'1'
then
time_counter
.
coarse
<=
regout
.
coarse
;
local_pps
<=
'0'
;
elsif
time_counter
.
coarse
=
std_logic_vector
(
c_TAG_COARSE_MAX
-
1
)
then
time_counter
.
coarse
<=
(
others
=>
'0'
);
...
...
hdl/rtl/timetag_core/Manifest.py
deleted
100644 → 0
View file @
e084c507
files
=
[
"timetag_core_regs.vhd"
,
"timetag_core_regs_wbgen2_pkg.vhd"
,
"timetag_core.vhd"
,
"timetag_core_pkg.vhd"
,
]
hdl/rtl/timetag_core/timetag_core_pkg.vhd
deleted
100644 → 0
View file @
e084c507
-------------------------------------------------------------------------------
-- Title : Timetag core package
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : timetag_core_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2019 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2013-07-05 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
package
timetag_core_pkg
is
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type
t_timetag
is
record
seconds
:
std_logic_vector
(
39
downto
0
);
coarse
:
std_logic_vector
(
27
downto
0
);
end
record
t_timetag
;
constant
c_TAG_COARSE_MAX
:
unsigned
:
=
to_unsigned
(
125000000
,
28
);
end
timetag_core_pkg
;
package
body
timetag_core_pkg
is
end
timetag_core_pkg
;
hdl/rtl/timetag_core/timetag_core_regs.vhd
deleted
100644 → 0
View file @
e084c507
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Time-tagging core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Fri Feb 23 15:43:42 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
timetag_core_wbgen2_pkg
.
all
;
entity
timetag_core_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_timetag_core_in_registers
;
regs_o
:
out
t_timetag_core_out_registers
);
end
timetag_core_regs
;
architecture
syn
of
timetag_core_regs
is
signal
timetag_core_time_trig_seconds_upper_int
:
std_logic_vector
(
7
downto
0
);
signal
timetag_core_time_trig_seconds_lower_int
:
std_logic_vector
(
31
downto
0
);
signal
timetag_core_time_trig_coarse_int
:
std_logic_vector
(
27
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
ack_in_progress
:
std_logic
;
begin
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
regs_o
.
seconds_upper_load_o
<=
'0'
;
regs_o
.
seconds_lower_load_o
<=
'0'
;
regs_o
.
coarse_load_o
<=
'0'
;
timetag_core_time_trig_seconds_upper_int
<=
"00000000"
;
timetag_core_time_trig_seconds_lower_int
<=
"00000000000000000000000000000000"
;
timetag_core_time_trig_coarse_int
<=
"0000000000000000000000000000"
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
regs_o
.
seconds_upper_load_o
<=
'0'
;
regs_o
.
seconds_lower_load_o
<=
'0'
;
regs_o
.
coarse_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
regs_o
.
seconds_upper_load_o
<=
'0'
;
regs_o
.
seconds_lower_load_o
<=
'0'
;
regs_o
.
coarse_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
4
downto
0
)
is
when
"00000"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
seconds_upper_load_o
<=
'1'
;
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
seconds_upper_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00001"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
seconds_lower_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
seconds_lower_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00010"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
coarse_load_o
<=
'1'
;
end
if
;
rddata_reg
(
27
downto
0
)
<=
regs_i
.
coarse_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00011"
=>
if
(
wb_we_i
=
'1'
)
then
timetag_core_time_trig_seconds_upper_int
<=
wrdata_reg
(
7
downto
0
);
end
if
;
rddata_reg
(
7
downto
0
)
<=
timetag_core_time_trig_seconds_upper_int
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00100"
=>
if
(
wb_we_i
=
'1'
)
then
timetag_core_time_trig_seconds_lower_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
31
downto
0
)
<=
timetag_core_time_trig_seconds_lower_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00101"
=>
if
(
wb_we_i
=
'1'
)
then
timetag_core_time_trig_coarse_int
<=
wrdata_reg
(
27
downto
0
);
end
if
;
rddata_reg
(
27
downto
0
)
<=
timetag_core_time_trig_coarse_int
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
trig_tag_seconds_upper_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
trig_tag_seconds_lower_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
27
downto
0
)
<=
regs_i
.
trig_tag_coarse_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01001"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
acq_start_tag_seconds_upper_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01010"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
acq_start_tag_seconds_lower_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
27
downto
0
)
<=
regs_i
.
acq_start_tag_coarse_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01100"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
acq_stop_tag_seconds_upper_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01101"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
acq_stop_tag_seconds_lower_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
27
downto
0
)
<=
regs_i
.
acq_stop_tag_coarse_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
acq_end_tag_seconds_upper_i
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
acq_end_tag_seconds_lower_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10001"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
27
downto
0
)
<=
regs_i
.
acq_end_tag_coarse_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- Timetag seconds
regs_o
.
seconds_upper_o
<=
wrdata_reg
(
7
downto
0
);
-- Timetag seconds
regs_o
.
seconds_lower_o
<=
wrdata_reg
(
31
downto
0
);
-- Timetag coarse time
regs_o
.
coarse_o
<=
wrdata_reg
(
27
downto
0
);
-- Time trigger seconds
regs_o
.
time_trig_seconds_upper_o
<=
timetag_core_time_trig_seconds_upper_int
;
-- Time trigger seconds
regs_o
.
time_trig_seconds_lower_o
<=
timetag_core_time_trig_seconds_lower_int
;
-- Time trigger coarse value
regs_o
.
time_trig_coarse_o
<=
timetag_core_time_trig_coarse_int
;
-- Trigger time-tag seconds
-- Trigger time-tag seconds
-- Trigger time-tag coarse time
-- Acquisition start time-tag seconds
-- Acquisition start time-tag seconds
-- Acquisition start time-tag coarse time
-- Acquisition stop time-tag seconds
-- Acquisition stop time-tag seconds
-- Acquisition stop time-tag coarse time
-- Acquisition end time-tag seconds
-- Acquisition end time-tag seconds
-- Acquisition end time-tag coarse time
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
hdl/rtl/timetag_core/timetag_core_regs_wbgen2_pkg.vhd
deleted
100644 → 0
View file @
e084c507
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Time-tagging core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Fri Feb 23 15:43:42 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
package
timetag_core_wbgen2_pkg
is
-- Input registers (user design -> WB slave)
type
t_timetag_core_in_registers
is
record
seconds_upper_i
:
std_logic_vector
(
7
downto
0
);
seconds_lower_i
:
std_logic_vector
(
31
downto
0
);
coarse_i
:
std_logic_vector
(
27
downto
0
);
trig_tag_seconds_upper_i
:
std_logic_vector
(
7
downto
0
);
trig_tag_seconds_lower_i
:
std_logic_vector
(
31
downto
0
);
trig_tag_coarse_i
:
std_logic_vector
(
27
downto
0
);
acq_start_tag_seconds_upper_i
:
std_logic_vector
(
7
downto
0
);
acq_start_tag_seconds_lower_i
:
std_logic_vector
(
31
downto
0
);
acq_start_tag_coarse_i
:
std_logic_vector
(
27
downto
0
);
acq_stop_tag_seconds_upper_i
:
std_logic_vector
(
7
downto
0
);
acq_stop_tag_seconds_lower_i
:
std_logic_vector
(
31
downto
0
);
acq_stop_tag_coarse_i
:
std_logic_vector
(
27
downto
0
);
acq_end_tag_seconds_upper_i
:
std_logic_vector
(
7
downto
0
);
acq_end_tag_seconds_lower_i
:
std_logic_vector
(
31
downto
0
);
acq_end_tag_coarse_i
:
std_logic_vector
(
27
downto
0
);
end
record
;
constant
c_timetag_core_in_registers_init_value
:
t_timetag_core_in_registers
:
=
(
seconds_upper_i
=>
(
others
=>
'0'
),
seconds_lower_i
=>
(
others
=>
'0'
),
coarse_i
=>
(
others
=>
'0'
),
trig_tag_seconds_upper_i
=>
(
others
=>
'0'
),
trig_tag_seconds_lower_i
=>
(
others
=>
'0'
),
trig_tag_coarse_i
=>
(
others
=>
'0'
),
acq_start_tag_seconds_upper_i
=>
(
others
=>
'0'
),
acq_start_tag_seconds_lower_i
=>
(
others
=>
'0'
),
acq_start_tag_coarse_i
=>
(
others
=>
'0'
),
acq_stop_tag_seconds_upper_i
=>
(
others
=>
'0'
),
acq_stop_tag_seconds_lower_i
=>
(
others
=>
'0'
),
acq_stop_tag_coarse_i
=>
(
others
=>
'0'
),
acq_end_tag_seconds_upper_i
=>
(
others
=>
'0'
),
acq_end_tag_seconds_lower_i
=>
(
others
=>
'0'
),
acq_end_tag_coarse_i
=>
(
others
=>
'0'
)
);
-- Output registers (WB slave -> user design)
type
t_timetag_core_out_registers
is
record
seconds_upper_o
:
std_logic_vector
(
7
downto
0
);
seconds_upper_load_o
:
std_logic
;
seconds_lower_o
:
std_logic_vector
(
31
downto
0
);
seconds_lower_load_o
:
std_logic
;
coarse_o
:
std_logic_vector
(
27
downto
0
);
coarse_load_o
:
std_logic
;
time_trig_seconds_upper_o
:
std_logic_vector
(
7
downto
0
);
time_trig_seconds_lower_o
:
std_logic_vector
(
31
downto
0
);
time_trig_coarse_o
:
std_logic_vector
(
27
downto
0
);
end
record
;
constant
c_timetag_core_out_registers_init_value
:
t_timetag_core_out_registers
:
=
(
seconds_upper_o
=>
(
others
=>
'0'
),
seconds_upper_load_o
=>
'0'
,
seconds_lower_o
=>
(
others
=>
'0'
),
seconds_lower_load_o
=>
'0'
,
coarse_o
=>
(
others
=>
'0'
),
coarse_load_o
=>
'0'
,
time_trig_seconds_upper_o
=>
(
others
=>
'0'
),
time_trig_seconds_lower_o
=>
(
others
=>
'0'
),
time_trig_coarse_o
=>
(
others
=>
'0'
)
);
function
"or"
(
left
,
right
:
t_timetag_core_in_registers
)
return
t_timetag_core_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
end
package
;
package
body
timetag_core_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
x
(
i
)
=
'1'
then
tmp
(
i
):
=
'1'
;
else
tmp
(
i
):
=
'0'
;
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_timetag_core_in_registers
)
return
t_timetag_core_in_registers
is
variable
tmp
:
t_timetag_core_in_registers
;
begin
tmp
.
seconds_upper_i
:
=
f_x_to_zero
(
left
.
seconds_upper_i
)
or
f_x_to_zero
(
right
.
seconds_upper_i
);
tmp
.
seconds_lower_i
:
=
f_x_to_zero
(
left
.
seconds_lower_i
)
or
f_x_to_zero
(
right
.
seconds_lower_i
);
tmp
.
coarse_i
:
=
f_x_to_zero
(
left
.
coarse_i
)
or
f_x_to_zero
(
right
.
coarse_i
);
tmp
.
trig_tag_seconds_upper_i
:
=
f_x_to_zero
(
left
.
trig_tag_seconds_upper_i
)
or
f_x_to_zero
(
right
.
trig_tag_seconds_upper_i
);
tmp
.
trig_tag_seconds_lower_i
:
=
f_x_to_zero
(
left
.
trig_tag_seconds_lower_i
)
or
f_x_to_zero
(
right
.
trig_tag_seconds_lower_i
);
tmp
.
trig_tag_coarse_i
:
=
f_x_to_zero
(
left
.
trig_tag_coarse_i
)
or
f_x_to_zero
(
right
.
trig_tag_coarse_i
);
tmp
.
acq_start_tag_seconds_upper_i
:
=
f_x_to_zero
(
left
.
acq_start_tag_seconds_upper_i
)
or
f_x_to_zero
(
right
.
acq_start_tag_seconds_upper_i
);
tmp
.
acq_start_tag_seconds_lower_i
:
=
f_x_to_zero
(
left
.
acq_start_tag_seconds_lower_i
)
or
f_x_to_zero
(
right
.
acq_start_tag_seconds_lower_i
);
tmp
.
acq_start_tag_coarse_i
:
=
f_x_to_zero
(
left
.
acq_start_tag_coarse_i
)
or
f_x_to_zero
(
right
.
acq_start_tag_coarse_i
);
tmp
.
acq_stop_tag_seconds_upper_i
:
=
f_x_to_zero
(
left
.
acq_stop_tag_seconds_upper_i
)
or
f_x_to_zero
(
right
.
acq_stop_tag_seconds_upper_i
);
tmp
.
acq_stop_tag_seconds_lower_i
:
=
f_x_to_zero
(
left
.
acq_stop_tag_seconds_lower_i
)
or
f_x_to_zero
(
right
.
acq_stop_tag_seconds_lower_i
);
tmp
.
acq_stop_tag_coarse_i
:
=
f_x_to_zero
(
left
.
acq_stop_tag_coarse_i
)
or
f_x_to_zero
(
right
.
acq_stop_tag_coarse_i
);
tmp
.
acq_end_tag_seconds_upper_i
:
=
f_x_to_zero
(
left
.
acq_end_tag_seconds_upper_i
)
or
f_x_to_zero
(
right
.
acq_end_tag_seconds_upper_i
);
tmp
.
acq_end_tag_seconds_lower_i
:
=
f_x_to_zero
(
left
.
acq_end_tag_seconds_lower_i
)
or
f_x_to_zero
(
right
.
acq_end_tag_seconds_lower_i
);
tmp
.
acq_end_tag_coarse_i
:
=
f_x_to_zero
(
left
.
acq_end_tag_coarse_i
)
or
f_x_to_zero
(
right
.
acq_end_tag_coarse_i
);
return
tmp
;
end
function
;
end
package
body
;
hdl/rtl/timetag_core/wb_gen/Makefile
deleted
100644 → 0
View file @
e084c507
WBGEN2
=
$(
shell
which wbgen2
)
RTL
=
../
TEX
=
../../../../doc/manual/
SIM
=
../../../testbench/include/
timetag_core_regs
:
$(WBGEN2)
-l
vhdl
-H
record
-V
$(RTL)$@
.vhd
-p
$(RTL)$@
_wbgen2_pkg.vhd
-f
html
-D
$@
.htm
-C
$@
.h
-K
$(SIM)$@
.v
$@
.wb
$(WBGEN2)
-f
texinfo
-D
$(TEX)$@
.tex
$@
.wb
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.h
deleted
100644 → 0
View file @
e084c507
/*
Register definitions for slave core: Time-tagging core registers
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Fri Feb 23 15:43:42 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB
#define __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Timetag seconds register (upper) */
/* definitions for register: Timetag seconds register (lower) */
/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
/* definitions for register: Time trigger seconds register (upper) */
/* definitions for register: Time trigger seconds register (lower) */
/* definitions for register: Time trigger coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag seconds register (upper) */
/* definitions for register: Trigger time-tag seconds register (lower) */
/* definitions for register: Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition start time-tag seconds register (upper) */
/* definitions for register: Acquisition start time-tag seconds register (lower) */
/* definitions for register: Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition stop time-tag seconds register (upper) */
/* definitions for register: Acquisition stop time-tag seconds register (lower) */
/* definitions for register: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition end time-tag seconds register (upper) */
/* definitions for register: Acquisition end time-tag seconds register (lower) */
/* definitions for register: Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
PACKED
struct
TIMETAG_CORE_WB
{
/* [0x0]: REG Timetag seconds register (upper) */
uint32_t
SECONDS_UPPER
;
/* [0x4]: REG Timetag seconds register (lower) */
uint32_t
SECONDS_LOWER
;
/* [0x8]: REG Timetag coarse time register, system clock ticks (125MHz) */
uint32_t
COARSE
;
/* [0xc]: REG Time trigger seconds register (upper) */
uint32_t
TIME_TRIG_SECONDS_UPPER
;
/* [0x10]: REG Time trigger seconds register (lower) */
uint32_t
TIME_TRIG_SECONDS_LOWER
;
/* [0x14]: REG Time trigger coarse time register, system clock ticks (125MHz) */
uint32_t
TIME_TRIG_COARSE
;
/* [0x18]: REG Trigger time-tag seconds register (upper) */
uint32_t
TRIG_TAG_SECONDS_UPPER
;
/* [0x1c]: REG Trigger time-tag seconds register (lower) */
uint32_t
TRIG_TAG_SECONDS_LOWER
;
/* [0x20]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
TRIG_TAG_COARSE
;
/* [0x24]: REG Acquisition start time-tag seconds register (upper) */
uint32_t
ACQ_START_TAG_SECONDS_UPPER
;
/* [0x28]: REG Acquisition start time-tag seconds register (lower) */
uint32_t
ACQ_START_TAG_SECONDS_LOWER
;
/* [0x2c]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
ACQ_START_TAG_COARSE
;
/* [0x30]: REG Acquisition stop time-tag seconds register (upper) */
uint32_t
ACQ_STOP_TAG_SECONDS_UPPER
;
/* [0x34]: REG Acquisition stop time-tag seconds register (lower) */
uint32_t
ACQ_STOP_TAG_SECONDS_LOWER
;
/* [0x38]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
ACQ_STOP_TAG_COARSE
;
/* [0x3c]: REG Acquisition end time-tag seconds register (upper) */
uint32_t
ACQ_END_TAG_SECONDS_UPPER
;
/* [0x40]: REG Acquisition end time-tag seconds register (lower) */
uint32_t
ACQ_END_TAG_SECONDS_LOWER
;
/* [0x44]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
ACQ_END_TAG_COARSE
;
};
#endif
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.htm
deleted
100644 → 0
View file @
e084c507
Changes suppressed. Click to show.
<HTML>
<HEAD>
<TITLE>
timetag_core_regs
</TITLE>
<STYLE
TYPE=
"text/css"
MEDIA=
"all"
>
<!--
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</STYLE>
</HEAD>
<BODY>
<h1
class=
"heading"
>
timetag_core_regs
</h1>
<h3>
Time-tagging core registers
</h3>
<p>
Wishbone slave for registers related to time-tagging core
</p>
<h3>
Contents:
</h3>
<span
style=
"margin-left: 0px; "
>
1.
<A
href=
"#sect_1_0"
>
Memory map summary
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
2.
<A
href=
"#sect_2_0"
>
HDL symbol
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
3.
<A
href=
"#sect_3_0"
>
Register description
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.1.
<A
href=
"#sect_3_1"
>
Timetag seconds register (upper)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.2.
<A
href=
"#sect_3_2"
>
Timetag seconds register (lower)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.3.
<A
href=
"#sect_3_3"
>
Timetag coarse time register, system clock ticks (125MHz)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.4.
<A
href=
"#sect_3_4"
>
Time trigger seconds register (upper)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.5.
<A
href=
"#sect_3_5"
>
Time trigger seconds register (lower)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.6.
<A
href=
"#sect_3_6"
>
Time trigger coarse time register, system clock ticks (125MHz)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.7.
<A
href=
"#sect_3_7"
>
Trigger time-tag seconds register (upper)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.8.
<A
href=
"#sect_3_8"
>
Trigger time-tag seconds register (lower)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.9.
<A
href=
"#sect_3_9"
>
Trigger time-tag coarse time (system clock ticks 125MHz) register
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.10.
<A
href=
"#sect_3_10"
>
Acquisition start time-tag seconds register (upper)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.11.
<A
href=
"#sect_3_11"
>
Acquisition start time-tag seconds register (lower)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.12.
<A
href=
"#sect_3_12"
>
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.13.
<A
href=
"#sect_3_13"
>
Acquisition stop time-tag seconds register (upper)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.14.
<A
href=
"#sect_3_14"
>
Acquisition stop time-tag seconds register (lower)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.15.
<A
href=
"#sect_3_15"
>
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.16.
<A
href=
"#sect_3_16"
>
Acquisition end time-tag seconds register (upper)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.17.
<A
href=
"#sect_3_17"
>
Acquisition end time-tag seconds register (lower)
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.18.
<A
href=
"#sect_3_18"
>
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
</a></span><br/>
<h3><a
name=
"sect_1_0"
>
1. Memory map summary
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<th
>
H/W Address
</th>
<th
>
Type
</th>
<th
>
Name
</th>
<th
>
VHDL/Verilog prefix
</th>
<th
>
C prefix
</th>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x0
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#SECONDS_UPPER"
>
Timetag seconds register (upper)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_seconds_upper
</td>
<td
class=
"td_code"
>
SECONDS_UPPER
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x1
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#SECONDS_LOWER"
>
Timetag seconds register (lower)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_seconds_lower
</td>
<td
class=
"td_code"
>
SECONDS_LOWER
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x2
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#COARSE"
>
Timetag coarse time register, system clock ticks (125MHz)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_coarse
</td>
<td
class=
"td_code"
>
COARSE
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x3
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#TIME_TRIG_SECONDS_UPPER"
>
Time trigger seconds register (upper)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_time_trig_seconds_upper
</td>
<td
class=
"td_code"
>
TIME_TRIG_SECONDS_UPPER
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x4
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#TIME_TRIG_SECONDS_LOWER"
>
Time trigger seconds register (lower)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_time_trig_seconds_lower
</td>
<td
class=
"td_code"
>
TIME_TRIG_SECONDS_LOWER
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x5
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#TIME_TRIG_COARSE"
>
Time trigger coarse time register, system clock ticks (125MHz)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_time_trig_coarse
</td>
<td
class=
"td_code"
>
TIME_TRIG_COARSE
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x6
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#TRIG_TAG_SECONDS_UPPER"
>
Trigger time-tag seconds register (upper)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_trig_tag_seconds_upper
</td>
<td
class=
"td_code"
>
TRIG_TAG_SECONDS_UPPER
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x7
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#TRIG_TAG_SECONDS_LOWER"
>
Trigger time-tag seconds register (lower)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_trig_tag_seconds_lower
</td>
<td
class=
"td_code"
>
TRIG_TAG_SECONDS_LOWER
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x8
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#TRIG_TAG_COARSE"
>
Trigger time-tag coarse time (system clock ticks 125MHz) register
</a>
</td>
<td
class=
"td_code"
>
timetag_core_trig_tag_coarse
</td>
<td
class=
"td_code"
>
TRIG_TAG_COARSE
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x9
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_START_TAG_SECONDS_UPPER"
>
Acquisition start time-tag seconds register (upper)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_start_tag_seconds_upper
</td>
<td
class=
"td_code"
>
ACQ_START_TAG_SECONDS_UPPER
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0xa
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_START_TAG_SECONDS_LOWER"
>
Acquisition start time-tag seconds register (lower)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_start_tag_seconds_lower
</td>
<td
class=
"td_code"
>
ACQ_START_TAG_SECONDS_LOWER
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0xb
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_START_TAG_COARSE"
>
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_start_tag_coarse
</td>
<td
class=
"td_code"
>
ACQ_START_TAG_COARSE
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0xc
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_STOP_TAG_SECONDS_UPPER"
>
Acquisition stop time-tag seconds register (upper)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_stop_tag_seconds_upper
</td>
<td
class=
"td_code"
>
ACQ_STOP_TAG_SECONDS_UPPER
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0xd
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_STOP_TAG_SECONDS_LOWER"
>
Acquisition stop time-tag seconds register (lower)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_stop_tag_seconds_lower
</td>
<td
class=
"td_code"
>
ACQ_STOP_TAG_SECONDS_LOWER
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0xe
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_STOP_TAG_COARSE"
>
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_stop_tag_coarse
</td>
<td
class=
"td_code"
>
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0xf
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_END_TAG_SECONDS_UPPER"
>
Acquisition end time-tag seconds register (upper)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_end_tag_seconds_upper
</td>
<td
class=
"td_code"
>
ACQ_END_TAG_SECONDS_UPPER
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x10
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_END_TAG_SECONDS_LOWER"
>
Acquisition end time-tag seconds register (lower)
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_end_tag_seconds_lower
</td>
<td
class=
"td_code"
>
ACQ_END_TAG_SECONDS_LOWER
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x11
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#ACQ_END_TAG_COARSE"
>
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
</a>
</td>
<td
class=
"td_code"
>
timetag_core_acq_end_tag_coarse
</td>
<td
class=
"td_code"
>
ACQ_END_TAG_COARSE
</td>
</tr>
</table>
<h3><a
name=
"sect_2_0"
>
2. HDL symbol
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
rst_n_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Timetag seconds register (upper):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
clk_sys_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_seconds_upper_o[7:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇒
</td>
<td
class=
"td_pblock_left"
>
wb_adr_i[4:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_seconds_upper_i[7:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇒
</td>
<td
class=
"td_pblock_left"
>
wb_dat_i[31:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_seconds_upper_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇐
</td>
<td
class=
"td_pblock_left"
>
wb_dat_o[31:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_cyc_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Timetag seconds register (lower):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
⇒
</td>
<td
class=
"td_pblock_left"
>
wb_sel_i[3:0]
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_seconds_lower_o[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_stb_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_seconds_lower_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_we_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_seconds_lower_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
←
</td>
<td
class=
"td_pblock_left"
>
wb_ack_o
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
←
</td>
<td
class=
"td_pblock_left"
>
wb_stall_o
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Timetag coarse time register, system clock ticks (125MHz):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_coarse_o[27:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_coarse_i[27:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_coarse_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Time trigger seconds register (upper):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_time_trig_seconds_upper_o[7:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Time trigger seconds register (lower):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_time_trig_seconds_lower_o[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Time trigger coarse time register, system clock ticks (125MHz):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_time_trig_coarse_o[27:0]
</td>
<td
class=
"td_arrow_right"
>
⇒
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Trigger time-tag seconds register (upper):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_trig_tag_seconds_upper_i[7:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Trigger time-tag seconds register (lower):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_trig_tag_seconds_lower_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Trigger time-tag coarse time (system clock ticks 125MHz) register:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_trig_tag_coarse_i[27:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition start time-tag seconds register (upper):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_start_tag_seconds_upper_i[7:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition start time-tag seconds register (lower):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_start_tag_seconds_lower_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition start time-tag coarse time (system clock ticks 125MHz) register:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_start_tag_coarse_i[27:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition stop time-tag seconds register (upper):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_stop_tag_seconds_upper_i[7:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition stop time-tag seconds register (lower):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_stop_tag_seconds_lower_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_stop_tag_coarse_i[27:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition end time-tag seconds register (upper):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_end_tag_seconds_upper_i[7:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition end time-tag seconds register (lower):
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_end_tag_seconds_lower_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Acquisition end time-tag coarse time (system clock ticks 125MHz) register:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
timetag_core_acq_end_tag_coarse_i[27:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
</table>
<h3><a
name=
"sect_3_0"
>
3. Register description
</a></h3>
<a
name=
"SECONDS_UPPER"
></a>
<h3><a
name=
"sect_3_1"
>
3.1. Timetag seconds register (upper)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_seconds_upper
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x0
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
SECONDS_UPPER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x0
</td>
</tr>
</table>
<p>
8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
SECONDS_UPPER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
SECONDS_UPPER
</b>
[
<i>
read/write
</i>
]: Timetag seconds
</ul>
<a
name=
"SECONDS_LOWER"
></a>
<h3><a
name=
"sect_3_2"
>
3.2. Timetag seconds register (lower)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_seconds_lower
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x1
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
SECONDS_LOWER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x4
</td>
</tr>
</table>
<p>
32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
SECONDS_LOWER[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
SECONDS_LOWER[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
SECONDS_LOWER[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
SECONDS_LOWER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
SECONDS_LOWER
</b>
[
<i>
read/write
</i>
]: Timetag seconds
</ul>
<a
name=
"COARSE"
></a>
<h3><a
name=
"sect_3_3"
>
3.3. Timetag coarse time register, system clock ticks (125MHz)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_coarse
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x2
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
COARSE
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x8
</td>
</tr>
</table>
<p>
Coarse time counter clocked by 125MHz system clock.
<br>
Counts from 0 to 125000000.
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
COARSE[27:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
COARSE[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
COARSE[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
COARSE[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
COARSE
</b>
[
<i>
read/write
</i>
]: Timetag coarse time
</ul>
<a
name=
"TIME_TRIG_SECONDS_UPPER"
></a>
<h3><a
name=
"sect_3_4"
>
3.4. Time trigger seconds register (upper)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_time_trig_seconds_upper
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x3
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
TIME_TRIG_SECONDS_UPPER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0xc
</td>
</tr>
</table>
<p>
8 upper bits of seconds used for timer trigger.
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_SECONDS_UPPER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
TIME_TRIG_SECONDS_UPPER
</b>
[
<i>
read/write
</i>
]: Time trigger seconds
</ul>
<a
name=
"TIME_TRIG_SECONDS_LOWER"
></a>
<h3><a
name=
"sect_3_5"
>
3.5. Time trigger seconds register (lower)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_time_trig_seconds_lower
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x4
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
TIME_TRIG_SECONDS_LOWER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x10
</td>
</tr>
</table>
<p>
32 lower bits of seconds used for time trigger.
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_SECONDS_LOWER[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_SECONDS_LOWER[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_SECONDS_LOWER[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_SECONDS_LOWER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
TIME_TRIG_SECONDS_LOWER
</b>
[
<i>
read/write
</i>
]: Time trigger seconds
</ul>
<a
name=
"TIME_TRIG_COARSE"
></a>
<h3><a
name=
"sect_3_6"
>
3.6. Time trigger coarse time register, system clock ticks (125MHz)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_time_trig_coarse
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x5
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
TIME_TRIG_COARSE
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x14
</td>
</tr>
</table>
<p>
Coarse time counter clocked by 125MHz system clock.
<br>
Counts from 0 to 125000000.
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
TIME_TRIG_COARSE[27:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_COARSE[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_COARSE[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TIME_TRIG_COARSE[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
TIME_TRIG_COARSE
</b>
[
<i>
read/write
</i>
]: Time trigger coarse value
</ul>
<a
name=
"TRIG_TAG_SECONDS_UPPER"
></a>
<h3><a
name=
"sect_3_7"
>
3.7. Trigger time-tag seconds register (upper)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_trig_tag_seconds_upper
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x6
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
TRIG_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x18
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_SECONDS_UPPER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_SECONDS_UPPER
</b>
[
<i>
read-only
</i>
]: Trigger time-tag seconds
<br>
Holds time-tag seconds of the last trigger event
</ul>
<a
name=
"TRIG_TAG_SECONDS_LOWER"
></a>
<h3><a
name=
"sect_3_8"
>
3.8. Trigger time-tag seconds register (lower)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_trig_tag_seconds_lower
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x7
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
TRIG_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x1c
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_SECONDS_LOWER[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_SECONDS_LOWER[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_SECONDS_LOWER[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_SECONDS_LOWER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_SECONDS_LOWER
</b>
[
<i>
read-only
</i>
]: Trigger time-tag seconds
<br>
Holds time-tag seconds of the last trigger event
</ul>
<a
name=
"TRIG_TAG_COARSE"
></a>
<h3><a
name=
"sect_3_9"
>
3.9. Trigger time-tag coarse time (system clock ticks 125MHz) register
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_trig_tag_coarse
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x8
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
TRIG_TAG_COARSE
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x20
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
TRIG_TAG_COARSE[27:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_COARSE[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_COARSE[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
TRIG_TAG_COARSE[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_COARSE
</b>
[
<i>
read-only
</i>
]: Trigger time-tag coarse time
<br>
Holds time-tag coarse time of the last trigger event
</ul>
<a
name=
"ACQ_START_TAG_SECONDS_UPPER"
></a>
<h3><a
name=
"sect_3_10"
>
3.10. Acquisition start time-tag seconds register (upper)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_start_tag_seconds_upper
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x9
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_START_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x24
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_SECONDS_UPPER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_SECONDS_UPPER
</b>
[
<i>
read-only
</i>
]: Acquisition start time-tag seconds
<br>
Holds time-tag seconds of the last acquisition start event
</ul>
<a
name=
"ACQ_START_TAG_SECONDS_LOWER"
></a>
<h3><a
name=
"sect_3_11"
>
3.11. Acquisition start time-tag seconds register (lower)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_start_tag_seconds_lower
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0xa
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_START_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x28
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_SECONDS_LOWER[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_SECONDS_LOWER[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_SECONDS_LOWER[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_SECONDS_LOWER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_SECONDS_LOWER
</b>
[
<i>
read-only
</i>
]: Acquisition start time-tag seconds
<br>
Holds time-tag seconds of the last acquisition start event
</ul>
<a
name=
"ACQ_START_TAG_COARSE"
></a>
<h3><a
name=
"sect_3_12"
>
3.12. Acquisition start time-tag coarse time (system clock ticks 125MHz) register
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_start_tag_coarse
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0xb
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_START_TAG_COARSE
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x2c
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
ACQ_START_TAG_COARSE[27:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_COARSE[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_COARSE[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_START_TAG_COARSE[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_COARSE
</b>
[
<i>
read-only
</i>
]: Acquisition start time-tag coarse time
<br>
Holds time-tag coarse time of the last acquisition start event
</ul>
<a
name=
"ACQ_STOP_TAG_SECONDS_UPPER"
></a>
<h3><a
name=
"sect_3_13"
>
3.13. Acquisition stop time-tag seconds register (upper)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_stop_tag_seconds_upper
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0xc
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_STOP_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x30
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_SECONDS_UPPER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_SECONDS_UPPER
</b>
[
<i>
read-only
</i>
]: Acquisition stop time-tag seconds
<br>
Holds time-tag seconds of the last acquisition stop event
</ul>
<a
name=
"ACQ_STOP_TAG_SECONDS_LOWER"
></a>
<h3><a
name=
"sect_3_14"
>
3.14. Acquisition stop time-tag seconds register (lower)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_stop_tag_seconds_lower
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0xd
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_STOP_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x34
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_SECONDS_LOWER[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_SECONDS_LOWER[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_SECONDS_LOWER[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_SECONDS_LOWER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_SECONDS_LOWER
</b>
[
<i>
read-only
</i>
]: Acquisition stop time-tag seconds
<br>
Holds time-tag seconds of the last acquisition stop event
</ul>
<a
name=
"ACQ_STOP_TAG_COARSE"
></a>
<h3><a
name=
"sect_3_15"
>
3.15. Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_stop_tag_coarse
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0xe
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x38
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
ACQ_STOP_TAG_COARSE[27:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_COARSE[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_COARSE[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_STOP_TAG_COARSE[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_COARSE
</b>
[
<i>
read-only
</i>
]: Acquisition stop time-tag coarse time
<br>
Holds time-tag coarse time of the last acquisition stop event
</ul>
<a
name=
"ACQ_END_TAG_SECONDS_UPPER"
></a>
<h3><a
name=
"sect_3_16"
>
3.16. Acquisition end time-tag seconds register (upper)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_end_tag_seconds_upper
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0xf
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_END_TAG_SECONDS_UPPER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x3c
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_SECONDS_UPPER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_END_TAG_SECONDS_UPPER
</b>
[
<i>
read-only
</i>
]: Acquisition end time-tag seconds
<br>
Holds time-tag seconds of the last acquisition end event
</ul>
<a
name=
"ACQ_END_TAG_SECONDS_LOWER"
></a>
<h3><a
name=
"sect_3_17"
>
3.17. Acquisition end time-tag seconds register (lower)
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_end_tag_seconds_lower
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x10
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_END_TAG_SECONDS_LOWER
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x40
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_SECONDS_LOWER[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_SECONDS_LOWER[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_SECONDS_LOWER[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_SECONDS_LOWER[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_END_TAG_SECONDS_LOWER
</b>
[
<i>
read-only
</i>
]: Acquisition end time-tag seconds
<br>
Holds time-tag seconds of the last acquisition end event
</ul>
<a
name=
"ACQ_END_TAG_COARSE"
></a>
<h3><a
name=
"sect_3_18"
>
3.18. Acquisition end time-tag coarse time (system clock ticks 125MHz) register
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
timetag_core_acq_end_tag_coarse
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x11
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
ACQ_END_TAG_COARSE
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x44
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
ACQ_END_TAG_COARSE[27:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_COARSE[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_COARSE[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
ACQ_END_TAG_COARSE[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_END_TAG_COARSE
</b>
[
<i>
read-only
</i>
]: Acquisition end time-tag coarse time
<br>
Holds time-tag coarse time of the last acquisition end event
</ul>
</BODY>
</HTML>
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.wb
deleted
100644 → 0
View file @
e084c507
peripheral {
name = "Time-tagging core registers";
description = "Wishbone slave for registers related to time-tagging core";
hdl_entity = "timetag_core_regs";
prefix = "timetag_core";
reg {
name = "Timetag seconds register (upper)";
description = "8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_upper";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag seconds register (lower)";
description = "32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_lower";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag coarse time register, system clock ticks (125MHz)";
description = "Coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "coarse";
field {
name = "Timetag coarse time";
type = SLV;
load = LOAD_EXT;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Time trigger seconds register (upper)";
description = "8 upper bits of seconds used for timer trigger.";
prefix = "time_trig_seconds_upper";
field {
name = "Time trigger seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Time trigger seconds register (lower)";
description = "32 lower bits of seconds used for time trigger.";
prefix = "time_trig_seconds_lower";
field {
name = "Time trigger seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Time trigger coarse time register, system clock ticks (125MHz)";
description = "Coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "time_trig_coarse";
field {
name = "Time trigger coarse value";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Trigger time-tag seconds register (upper)";
prefix = "trig_tag_seconds_upper";
field {
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag seconds register (lower)";
prefix = "trig_tag_seconds_lower";
field {
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag coarse time (system clock ticks 125MHz) register";
prefix = "trig_tag_coarse";
field {
name = "Trigger time-tag coarse time";
description = "Holds time-tag coarse time of the last trigger event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag seconds register (upper)";
prefix = "acq_start_tag_seconds_upper";
field {
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag seconds register (lower)";
prefix = "acq_start_tag_seconds_lower";
field {
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_start_tag_coarse";
field {
name = "Acquisition start time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition start event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag seconds register (upper)";
prefix = "acq_stop_tag_seconds_upper";
field {
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag seconds register (lower)";
prefix = "acq_stop_tag_seconds_lower";
field {
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_stop_tag_coarse";
field {
name = "Acquisition stop time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition stop event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag seconds register (upper)";
prefix = "acq_end_tag_seconds_upper";
field {
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag seconds register (lower)";
prefix = "acq_end_tag_seconds_lower";
field {
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_end_tag_coarse";
field {
name = "Acquisition end time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition end event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/rtl/timetag_core_regs.cheby
0 → 100644
View file @
3501364d
memory-map:
bus: wb-32-be
name: timetag_core_regs
description: Time-tagging core registers
comment: |
Wishbone slave for registers related to time-tagging core
x-hdl:
busgroup: True
iogroup: timetag_core
children:
- reg:
name: seconds_upper
address: 0x00000000
width: 32
access: rw
description: Timetag seconds register (upper)
x-hdl:
write-strobe: True
comment: |
8 upper bits of seconds counter. Incremented every time the coarse counter overflows.
children:
- field:
name: ""
range: 7-0
description: Timetag seconds
x-hdl:
type: wire
- reg:
name: seconds_lower
address: 0x00000004
width: 32
access: rw
description: Timetag seconds register (lower)
x-hdl:
write-strobe: True
type: wire
comment: |
32 lower bits of seconds counter. Incremented every time the coarse counter overflows.
- reg:
name: coarse
address: 0x00000008
width: 32
access: rw
description: Timetag coarse time register, system clock ticks (125MHz)
x-hdl:
write-strobe: True
comment: |
Coarse time counter clocked by 125MHz system clock.
Counts from 0 to 125000000.
children:
- field:
name: ""
range: 27-0
description: Timetag coarse time
x-hdl:
type: wire
- reg:
name: time_trig_seconds_upper
address: 0x0000000c
width: 32
access: rw
description: Time trigger seconds register (upper)
comment: |
8 upper bits of seconds used for timer trigger.
children:
- field:
name: ""
range: 7-0
description: Time trigger seconds
- reg:
name: time_trig_seconds_lower
address: 0x00000010
width: 32
access: rw
description: Time trigger seconds register (lower)
comment: |
32 lower bits of seconds used for time trigger.
- reg:
name: time_trig_coarse
address: 0x00000014
width: 32
access: rw
description: Time trigger coarse time register, system clock ticks (125MHz)
comment: |
Coarse time counter clocked by 125MHz system clock.
Counts from 0 to 125000000.
children:
- field:
name: ""
range: 27-0
description: Time trigger coarse value
- reg:
name: trig_tag_seconds_upper
address: 0x00000018
width: 32
access: ro
description: Trigger time-tag seconds register (upper)
children:
- field:
name: ""
range: 7-0
description: Trigger time-tag seconds
comment: |
Holds time-tag seconds of the last trigger event
- reg:
name: trig_tag_seconds_lower
address: 0x0000001c
width: 32
access: ro
description: Trigger time-tag seconds register (lower)
comment: |
Holds time-tag seconds of the last trigger event
- reg:
name: trig_tag_coarse
address: 0x00000020
width: 32
access: ro
description: Trigger time-tag coarse time (system clock ticks 125MHz) register
children:
- field:
name: ""
range: 27-0
description: Trigger time-tag coarse time
comment: |
Holds time-tag coarse time of the last trigger event
- reg:
name: acq_start_tag_seconds_upper
address: 0x00000024
width: 32
access: ro
description: Acquisition start time-tag seconds register (upper)
children:
- field:
name: ""
range: 7-0
description: Acquisition start time-tag seconds
comment: |
Holds time-tag seconds of the last acquisition start event
- reg:
name: acq_start_tag_seconds_lower
address: 0x00000028
width: 32
access: ro
description: Acquisition start time-tag seconds register (lower)
comment: |
Holds time-tag seconds of the last acquisition start event
- reg:
name: acq_start_tag_coarse
address: 0x0000002c
width: 32
access: ro
description: Acquisition start time-tag coarse time (system clock ticks 125MHz) register
children:
- field:
name: ""
range: 27-0
description: Acquisition start time-tag coarse time
comment: |
Holds time-tag coarse time of the last acquisition start event
- reg:
name: acq_stop_tag_seconds_upper
address: 0x00000030
width: 32
access: ro
description: Acquisition stop time-tag seconds register (upper)
children:
- field:
name: ""
range: 7-0
description: Acquisition stop time-tag seconds
comment: |
Holds time-tag seconds of the last acquisition stop event
- reg:
name: acq_stop_tag_seconds_lower
address: 0x00000034
width: 32
access: ro
description: Acquisition stop time-tag seconds register (lower)
comment: |
Holds time-tag seconds of the last acquisition stop event
- reg:
name: acq_stop_tag_coarse
address: 0x00000038
width: 32
access: ro
description: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
children:
- field:
name: ""
range: 27-0
description: Acquisition stop time-tag coarse time
comment: |
Holds time-tag coarse time of the last acquisition stop event
- reg:
name: acq_end_tag_seconds_upper
address: 0x0000003c
width: 32
access: ro
description: Acquisition end time-tag seconds register (upper)
children:
- field:
name: ""
range: 7-0
description: Acquisition end time-tag seconds
comment: |
Holds time-tag seconds of the last acquisition end event
- reg:
name: acq_end_tag_seconds_lower
address: 0x00000040
width: 32
access: ro
description: Acquisition end time-tag seconds register (lower)
comment: |
Holds time-tag seconds of the last acquisition end event
- reg:
name: acq_end_tag_coarse
address: 0x00000044
width: 32
access: ro
description: Acquisition end time-tag coarse time (system clock ticks 125MHz) register
children:
- field:
name: ""
range: 27-0
description: Acquisition end time-tag coarse time
comment: |
Holds time-tag coarse time of the last acquisition end event
hdl/rtl/timetag_core_regs.vhd
0 → 100644
View file @
3501364d
-- Do not edit; this file was generated by Cheby using these options:
-- -i timetag_core_regs.cheby --gen-hdl=timetag_core_regs.vhd
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
timetag_core_regs_pkg
is
type
t_timetag_core_master_out
is
record
seconds_upper
:
std_logic_vector
(
7
downto
0
);
seconds_upper_wr
:
std_logic
;
seconds_lower
:
std_logic_vector
(
31
downto
0
);
seconds_lower_wr
:
std_logic
;
coarse
:
std_logic_vector
(
27
downto
0
);
coarse_wr
:
std_logic
;
time_trig_seconds_upper
:
std_logic_vector
(
7
downto
0
);
time_trig_seconds_lower
:
std_logic_vector
(
31
downto
0
);
time_trig_coarse
:
std_logic_vector
(
27
downto
0
);
end
record
t_timetag_core_master_out
;
subtype
t_timetag_core_slave_in
is
t_timetag_core_master_out
;
type
t_timetag_core_slave_out
is
record
seconds_upper
:
std_logic_vector
(
7
downto
0
);
seconds_lower
:
std_logic_vector
(
31
downto
0
);
coarse
:
std_logic_vector
(
27
downto
0
);
trig_tag_seconds_upper
:
std_logic_vector
(
7
downto
0
);
trig_tag_seconds_lower
:
std_logic_vector
(
31
downto
0
);
trig_tag_coarse
:
std_logic_vector
(
27
downto
0
);
acq_start_tag_seconds_upper
:
std_logic_vector
(
7
downto
0
);
acq_start_tag_seconds_lower
:
std_logic_vector
(
31
downto
0
);
acq_start_tag_coarse
:
std_logic_vector
(
27
downto
0
);
acq_stop_tag_seconds_upper
:
std_logic_vector
(
7
downto
0
);
acq_stop_tag_seconds_lower
:
std_logic_vector
(
31
downto
0
);
acq_stop_tag_coarse
:
std_logic_vector
(
27
downto
0
);
acq_end_tag_seconds_upper
:
std_logic_vector
(
7
downto
0
);
acq_end_tag_seconds_lower
:
std_logic_vector
(
31
downto
0
);
acq_end_tag_coarse
:
std_logic_vector
(
27
downto
0
);
end
record
t_timetag_core_slave_out
;
subtype
t_timetag_core_master_in
is
t_timetag_core_slave_out
;
end
timetag_core_regs_pkg
;
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
timetag_core_regs_pkg
.
all
;
entity
timetag_core_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
;
-- Wires and registers
timetag_core_i
:
in
t_timetag_core_master_in
;
timetag_core_o
:
out
t_timetag_core_master_out
);
end
timetag_core_regs
;
architecture
syn
of
timetag_core_regs
is
signal
rd_int
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_ack_int
:
std_logic
;
signal
wr_ack_int
:
std_logic
;
signal
wb_en
:
std_logic
;
signal
ack_int
:
std_logic
;
signal
wb_rip
:
std_logic
;
signal
wb_wip
:
std_logic
;
signal
time_trig_seconds_upper_reg
:
std_logic_vector
(
7
downto
0
);
signal
time_trig_seconds_lower_reg
:
std_logic_vector
(
31
downto
0
);
signal
time_trig_coarse_reg
:
std_logic_vector
(
27
downto
0
);
signal
reg_rdat_int
:
std_logic_vector
(
31
downto
0
);
signal
rd_ack1_int
:
std_logic
;
begin
-- WB decode signals
wb_en
<=
wb_i
.
cyc
and
wb_i
.
stb
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_rip
<=
'0'
;
else
wb_rip
<=
(
wb_rip
or
(
wb_en
and
not
wb_i
.
we
))
and
not
rd_ack_int
;
end
if
;
end
if
;
end
process
;
rd_int
<=
(
wb_en
and
not
wb_i
.
we
)
and
not
wb_rip
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_wip
<=
'0'
;
else
wb_wip
<=
(
wb_wip
or
(
wb_en
and
wb_i
.
we
))
and
not
wr_ack_int
;
end
if
;
end
if
;
end
process
;
wr_int
<=
(
wb_en
and
wb_i
.
we
)
and
not
wb_wip
;
ack_int
<=
rd_ack_int
or
wr_ack_int
;
wb_o
.
ack
<=
ack_int
;
wb_o
.
stall
<=
not
ack_int
and
wb_en
;
wb_o
.
rty
<=
'0'
;
wb_o
.
err
<=
'0'
;
-- Assign outputs
timetag_core_o
.
time_trig_seconds_upper
<=
time_trig_seconds_upper_reg
;
timetag_core_o
.
time_trig_seconds_lower
<=
time_trig_seconds_lower_reg
;
timetag_core_o
.
time_trig_coarse
<=
time_trig_coarse_reg
;
-- Process for write requests.
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wr_ack_int
<=
'0'
;
timetag_core_o
.
seconds_upper_wr
<=
'0'
;
timetag_core_o
.
seconds_lower_wr
<=
'0'
;
timetag_core_o
.
coarse_wr
<=
'0'
;
time_trig_seconds_upper_reg
<=
"00000000"
;
time_trig_seconds_lower_reg
<=
"00000000000000000000000000000000"
;
time_trig_coarse_reg
<=
"0000000000000000000000000000"
;
else
wr_ack_int
<=
'0'
;
timetag_core_o
.
seconds_upper_wr
<=
'0'
;
timetag_core_o
.
seconds_lower_wr
<=
'0'
;
timetag_core_o
.
coarse_wr
<=
'0'
;
case
wb_i
.
adr
(
6
downto
2
)
is
when
"00000"
=>
-- Register seconds_upper
timetag_core_o
.
seconds_upper_wr
<=
wr_int
;
if
wr_int
=
'1'
then
timetag_core_o
.
seconds_upper
<=
wb_i
.
dat
(
7
downto
0
);
end
if
;
wr_ack_int
<=
wr_int
;
when
"00001"
=>
-- Register seconds_lower
timetag_core_o
.
seconds_lower_wr
<=
wr_int
;
if
wr_int
=
'1'
then
timetag_core_o
.
seconds_lower
<=
wb_i
.
dat
;
end
if
;
wr_ack_int
<=
wr_int
;
when
"00010"
=>
-- Register coarse
timetag_core_o
.
coarse_wr
<=
wr_int
;
if
wr_int
=
'1'
then
timetag_core_o
.
coarse
<=
wb_i
.
dat
(
27
downto
0
);
end
if
;
wr_ack_int
<=
wr_int
;
when
"00011"
=>
-- Register time_trig_seconds_upper
if
wr_int
=
'1'
then
time_trig_seconds_upper_reg
<=
wb_i
.
dat
(
7
downto
0
);
end
if
;
wr_ack_int
<=
wr_int
;
when
"00100"
=>
-- Register time_trig_seconds_lower
if
wr_int
=
'1'
then
time_trig_seconds_lower_reg
<=
wb_i
.
dat
;
end
if
;
wr_ack_int
<=
wr_int
;
when
"00101"
=>
-- Register time_trig_coarse
if
wr_int
=
'1'
then
time_trig_coarse_reg
<=
wb_i
.
dat
(
27
downto
0
);
end
if
;
wr_ack_int
<=
wr_int
;
when
"00110"
=>
-- Register trig_tag_seconds_upper
when
"00111"
=>
-- Register trig_tag_seconds_lower
when
"01000"
=>
-- Register trig_tag_coarse
when
"01001"
=>
-- Register acq_start_tag_seconds_upper
when
"01010"
=>
-- Register acq_start_tag_seconds_lower
when
"01011"
=>
-- Register acq_start_tag_coarse
when
"01100"
=>
-- Register acq_stop_tag_seconds_upper
when
"01101"
=>
-- Register acq_stop_tag_seconds_lower
when
"01110"
=>
-- Register acq_stop_tag_coarse
when
"01111"
=>
-- Register acq_end_tag_seconds_upper
when
"10000"
=>
-- Register acq_end_tag_seconds_lower
when
"10001"
=>
-- Register acq_end_tag_coarse
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
end
if
;
end
if
;
end
process
;
-- Process for registers read.
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
rd_ack1_int
<=
'0'
;
else
reg_rdat_int
<=
(
others
=>
'0'
);
case
wb_i
.
adr
(
6
downto
2
)
is
when
"00000"
=>
-- seconds_upper
reg_rdat_int
(
7
downto
0
)
<=
timetag_core_i
.
seconds_upper
;
rd_ack1_int
<=
rd_int
;
when
"00001"
=>
-- seconds_lower
reg_rdat_int
<=
timetag_core_i
.
seconds_lower
;
rd_ack1_int
<=
rd_int
;
when
"00010"
=>
-- coarse
reg_rdat_int
(
27
downto
0
)
<=
timetag_core_i
.
coarse
;
rd_ack1_int
<=
rd_int
;
when
"00011"
=>
-- time_trig_seconds_upper
reg_rdat_int
(
7
downto
0
)
<=
time_trig_seconds_upper_reg
;
rd_ack1_int
<=
rd_int
;
when
"00100"
=>
-- time_trig_seconds_lower
reg_rdat_int
<=
time_trig_seconds_lower_reg
;
rd_ack1_int
<=
rd_int
;
when
"00101"
=>
-- time_trig_coarse
reg_rdat_int
(
27
downto
0
)
<=
time_trig_coarse_reg
;
rd_ack1_int
<=
rd_int
;
when
"00110"
=>
-- trig_tag_seconds_upper
reg_rdat_int
(
7
downto
0
)
<=
timetag_core_i
.
trig_tag_seconds_upper
;
rd_ack1_int
<=
rd_int
;
when
"00111"
=>
-- trig_tag_seconds_lower
reg_rdat_int
<=
timetag_core_i
.
trig_tag_seconds_lower
;
rd_ack1_int
<=
rd_int
;
when
"01000"
=>
-- trig_tag_coarse
reg_rdat_int
(
27
downto
0
)
<=
timetag_core_i
.
trig_tag_coarse
;
rd_ack1_int
<=
rd_int
;
when
"01001"
=>
-- acq_start_tag_seconds_upper
reg_rdat_int
(
7
downto
0
)
<=
timetag_core_i
.
acq_start_tag_seconds_upper
;
rd_ack1_int
<=
rd_int
;
when
"01010"
=>
-- acq_start_tag_seconds_lower
reg_rdat_int
<=
timetag_core_i
.
acq_start_tag_seconds_lower
;
rd_ack1_int
<=
rd_int
;
when
"01011"
=>
-- acq_start_tag_coarse
reg_rdat_int
(
27
downto
0
)
<=
timetag_core_i
.
acq_start_tag_coarse
;
rd_ack1_int
<=
rd_int
;
when
"01100"
=>
-- acq_stop_tag_seconds_upper
reg_rdat_int
(
7
downto
0
)
<=
timetag_core_i
.
acq_stop_tag_seconds_upper
;
rd_ack1_int
<=
rd_int
;
when
"01101"
=>
-- acq_stop_tag_seconds_lower
reg_rdat_int
<=
timetag_core_i
.
acq_stop_tag_seconds_lower
;
rd_ack1_int
<=
rd_int
;
when
"01110"
=>
-- acq_stop_tag_coarse
reg_rdat_int
(
27
downto
0
)
<=
timetag_core_i
.
acq_stop_tag_coarse
;
rd_ack1_int
<=
rd_int
;
when
"01111"
=>
-- acq_end_tag_seconds_upper
reg_rdat_int
(
7
downto
0
)
<=
timetag_core_i
.
acq_end_tag_seconds_upper
;
rd_ack1_int
<=
rd_int
;
when
"10000"
=>
-- acq_end_tag_seconds_lower
reg_rdat_int
<=
timetag_core_i
.
acq_end_tag_seconds_lower
;
rd_ack1_int
<=
rd_int
;
when
"10001"
=>
-- acq_end_tag_coarse
reg_rdat_int
(
27
downto
0
)
<=
timetag_core_i
.
acq_end_tag_coarse
;
rd_ack1_int
<=
rd_int
;
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
end
if
;
end
if
;
end
process
;
-- Process for read requests.
process
(
wb_i
.
adr
,
reg_rdat_int
,
rd_ack1_int
,
rd_int
)
begin
-- By default ack read requests
wb_o
.
dat
<=
(
others
=>
'0'
);
case
wb_i
.
adr
(
6
downto
2
)
is
when
"00000"
=>
-- seconds_upper
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"00001"
=>
-- seconds_lower
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"00010"
=>
-- coarse
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"00011"
=>
-- time_trig_seconds_upper
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"00100"
=>
-- time_trig_seconds_lower
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"00101"
=>
-- time_trig_coarse
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"00110"
=>
-- trig_tag_seconds_upper
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"00111"
=>
-- trig_tag_seconds_lower
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01000"
=>
-- trig_tag_coarse
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01001"
=>
-- acq_start_tag_seconds_upper
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01010"
=>
-- acq_start_tag_seconds_lower
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01011"
=>
-- acq_start_tag_coarse
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01100"
=>
-- acq_stop_tag_seconds_upper
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01101"
=>
-- acq_stop_tag_seconds_lower
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01110"
=>
-- acq_stop_tag_coarse
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01111"
=>
-- acq_end_tag_seconds_upper
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"10000"
=>
-- acq_end_tag_seconds_lower
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"10001"
=>
-- acq_end_tag_coarse
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
end
process
;
end
syn
;
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @
3501364d
...
...
@@ -248,9 +248,9 @@ module main;
#
1u
s
;
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_SECONDS_UPPER
,
'h00000032
)
;
// timetag core seconds high
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_SECONDS_LOWER
,
'h00005a34
)
;
// timetag core seconds low
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_COARSE
,
'h00000000
)
;
// timetag core ticks
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_
REGS_
SECONDS_UPPER
,
'h00000032
)
;
// timetag core seconds high
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_
REGS_
SECONDS_LOWER
,
'h00005a34
)
;
// timetag core seconds low
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_
REGS_
COARSE
,
'h00000000
)
;
// timetag core ticks
wait
(
acq_fsm_state
==
1
)
;
$
display
(
"<%t> START ACQ 1"
,
$
realtime
)
;
...
...
@@ -313,11 +313,11 @@ module main;
#
1u
s
;
// set time trigger
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_UPPER
,
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_
REGS_
TIME_TRIG_SECONDS_UPPER
,
'h00000032
)
;
// timetag core seconds high
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_LOWER
,
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_
REGS_
TIME_TRIG_SECONDS_LOWER
,
'h00005a34
)
;
// timetag core seconds low
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_TIME_TRIG_COARSE
,
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_
REGS_
TIME_TRIG_COARSE
,
'h00000e00
)
;
// timetag core ticks
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00000010
)
;
...
...
@@ -358,7 +358,7 @@ module main;
// set time trigger
trigin_acc
.
write
(
`ADDR_ALT_TRIGIN_SECONDS
+
0
,
'h00000032
)
;
trigin_acc
.
write
(
`ADDR_ALT_TRIGIN_SECONDS
+
4
,
'h00005a34
)
;
acc
.
read
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_TIME_TRIG_COARSE
,
val
)
;
acc
.
read
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_
REGS_
TIME_TRIG_COARSE
,
val
)
;
trigin_acc
.
write
(
`ADDR_ALT_TRIGIN_CYCLES
,
val
+
'h00001000
)
;
trigin_acc
.
write
(
`ADDR_ALT_TRIGIN_CTRL
,
`ALT_TRIGIN_CTRL_ENABLE
)
;
...
...
hdl/testbench/include/timetag_core_regs.v
View file @
3501364d
`define
ADDR_TIMETAG_CORE_SECONDS_UPPER
7'h0
`define
ADDR_TIMETAG_CORE_SECONDS_LOWER 7
'
h4
`define
ADDR_TIMETAG_CORE_COARSE 7
'
h8
`define
ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_UPPER 7
'
hc
`define
ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_LOWER 7
'
h10
`define
ADDR_TIMETAG_CORE_TIME_TRIG_COARSE 7
'
h14
`define
ADDR_TIMETAG_CORE_TRIG_TAG_SECONDS_UPPER 7
'
h18
`define
ADDR_TIMETAG_CORE_TRIG_TAG_SECONDS_LOWER 7
'
h1c
`define
ADDR_TIMETAG_CORE_TRIG_TAG_COARSE 7
'
h20
`define
ADDR_TIMETAG_CORE_ACQ_START_TAG_SECONDS_UPPER 7
'
h24
`define
ADDR_TIMETAG_CORE_ACQ_START_TAG_SECONDS_LOWER 7
'
h28
`define
ADDR_TIMETAG_CORE_ACQ_START_TAG_COARSE 7
'
h2c
`define
ADDR_TIMETAG_CORE_ACQ_STOP_TAG_SECONDS_UPPER 7
'
h30
`define
ADDR_TIMETAG_CORE_ACQ_STOP_TAG_SECONDS_LOWER 7
'
h34
`define
ADDR_TIMETAG_CORE_ACQ_STOP_TAG_COARSE 7
'
h38
`define
ADDR_TIMETAG_CORE_ACQ_END_TAG_SECONDS_UPPER 7
'
h3c
`define
ADDR_TIMETAG_CORE_ACQ_END_TAG_SECONDS_LOWER 7
'
h40
`define
ADDR_TIMETAG_CORE_ACQ_END_TAG_COARSE 7
'
h44
`define
TIMETAG_CORE_REGS_SIZE
72
`define
ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER
'
h0
`define
TIMETAG_CORE_REGS_SECONDS_UPPER_OFFSET 0
`define
TIMETAG_CORE_REGS_SECONDS_UPPER
'
hff
`define
ADDR_TIMETAG_CORE_REGS_SECONDS_LOWER
'
h4
`define
ADDR_TIMETAG_CORE_REGS_COARSE
'
h8
`define
TIMETAG_CORE_REGS_COARSE_OFFSET 0
`define
TIMETAG_CORE_REGS_COARSE
'
hfffffff
`define
ADDR_TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER
'
hc
`define
TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER_OFFSET 0
`define
TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER
'
hff
`define
ADDR_TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_LOWER
'
h10
`define
ADDR_TIMETAG_CORE_REGS_TIME_TRIG_COARSE
'
h14
`define
TIMETAG_CORE_REGS_TIME_TRIG_COARSE_OFFSET 0
`define
TIMETAG_CORE_REGS_TIME_TRIG_COARSE
'
hfffffff
`define
ADDR_TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER
'
h18
`define
TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER_OFFSET 0
`define
TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER
'
hff
`define
ADDR_TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_LOWER
'
h1c
`define
ADDR_TIMETAG_CORE_REGS_TRIG_TAG_COARSE
'
h20
`define
TIMETAG_CORE_REGS_TRIG_TAG_COARSE_OFFSET 0
`define
TIMETAG_CORE_REGS_TRIG_TAG_COARSE
'
hfffffff
`define
ADDR_TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER
'
h24
`define
TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER_OFFSET 0
`define
TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER
'
hff
`define
ADDR_TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_LOWER
'
h28
`define
ADDR_TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE
'
h2c
`define
TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE_OFFSET 0
`define
TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE
'
hfffffff
`define
ADDR_TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER
'
h30
`define
TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER_OFFSET 0
`define
TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER
'
hff
`define
ADDR_TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_LOWER
'
h34
`define
ADDR_TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE
'
h38
`define
TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE_OFFSET 0
`define
TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE
'
hfffffff
`define
ADDR_TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER
'
h3c
`define
TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER_OFFSET 0
`define
TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER
'
hff
`define
ADDR_TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_LOWER
'
h40
`define
ADDR_TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE
'
h44
`define
TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE_OFFSET 0
`define
TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE
'
hfffffff
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @
3501364d
...
...
@@ -41,7 +41,6 @@ use work.gencores_pkg.all;
use
work
.
wishbone_pkg
.
all
;
use
work
.
fmc_adc_mezzanine_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
use
work
.
timetag_core_pkg
.
all
;
use
work
.
carrier_csr_wbgen2_pkg
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
...
...
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @
3501364d
...
...
@@ -41,7 +41,6 @@ use work.gencores_pkg.all;
use
work
.
wishbone_pkg
.
all
;
use
work
.
fmc_adc_mezzanine_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
use
work
.
timetag_core_pkg
.
all
;
use
work
.
carrier_csr_wbgen2_pkg
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
...
...
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