Commit 3501364d authored by Dimitris Lampridis's avatar Dimitris Lampridis

Migrate Timetag Core to Cheby

parent e084c507
This diff is collapsed.
......@@ -8,10 +8,6 @@ files = [
"fmc_adc_alt_trigout.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd",
"timetag_core_regs.vhd",
"timetag_core.vhd",
]
modules = {
"local" : [
"timetag_core",
],
}
......@@ -33,7 +33,7 @@ library unisim;
use unisim.vcomponents.all;
library work;
use work.timetag_core_pkg.all;
use work.timetag_core_defs_pkg.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
......
......@@ -35,7 +35,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
use work.timetag_core_defs_pkg.all;
use work.wishbone_pkg.all;
package fmc_adc_100Ms_core_pkg is
......
......@@ -34,8 +34,8 @@ use IEEE.NUMERIC_STD.all;
library work;
use work.fmc_adc_100Ms_core_pkg.all;
use work.wishbone_pkg.all;
use work.timetag_core_pkg.all;
use work.timetag_core_regs_pkg.all;
use work.timetag_core_defs_pkg.all;
entity fmc_adc_mezzanine is
generic (
......@@ -592,9 +592,11 @@ begin
------------------------------------------------------------------------------
cmp_timetag_core : entity work.timetag_core
generic map (
g_WB_MODE => PIPELINED,
g_WB_GRANULARITY => BYTE,
-- Systematic delay introduced to the time tag by the FMC-ADC-100M core.
-- Measured experimentally.
g_TAG_ADJUST => g_TAG_ADJUST)
g_TAG_ADJUST => g_TAG_ADJUST)
port map(
clk_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
......@@ -619,15 +621,8 @@ begin
alt_trigin_tag_i => alt_trigin_tag,
alt_trigin_o => alt_time_trigger,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_TIMETAG).ack
);
wb_i => cnx_slave_in(c_WB_SLAVE_TIMETAG),
wb_o => cnx_slave_out(c_WB_SLAVE_TIMETAG));
cmp_alt_trigin : entity work.alt_trigin
port map (
......@@ -647,9 +642,4 @@ begin
alt_trigin_tag <= (seconds => alt_trigin_secs(39 downto 0),
coarse => alt_trigin_cycs(27 downto 0));
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_TIMETAG).err <= '0';
cnx_slave_out(c_WB_SLAVE_TIMETAG).rty <= '0';
cnx_slave_out(c_WB_SLAVE_TIMETAG).stall <= '0';
end rtl;
......@@ -34,7 +34,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
use work.timetag_core_defs_pkg.all;
use work.wishbone_pkg.all;
package fmc_adc_mezzanine_pkg is
......
......@@ -4,8 +4,6 @@
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : timetag_core.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-11-18
-- Standard : VHDL'93/02
......@@ -27,26 +25,42 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2011-11-18 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
use work.timetag_core_wbgen2_pkg.all;
package timetag_core_defs_pkg is
type t_timetag is record
seconds : std_logic_vector(39 downto 0);
coarse : std_logic_vector(27 downto 0);
end record t_timetag;
constant c_TAG_COARSE_MAX : unsigned := to_unsigned(125000000, 28);
end timetag_core_defs_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wishbone_pkg.all;
use work.timetag_core_regs_pkg.all;
use work.timetag_core_defs_pkg.all;
entity timetag_core is
generic (
-- WB interface configuration
g_WB_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_GRANULARITY : t_wishbone_address_granularity := BYTE;
-- Value to be subtracted from trigger tag coarse counter.
-- This is useful if you know that the system introduces
-- some systematic delay wrt the actual trigger time
g_TAG_ADJUST : natural := 0);
g_TAG_ADJUST : natural := 0);
port (
-- Clock, reset
clk_i : in std_logic; -- Must be 125MHz
clk_i : in std_logic; -- Must be 125MHz
rst_n_i : in std_logic;
-- Input pulses to time-tag
......@@ -75,41 +89,12 @@ entity timetag_core is
alt_trigin_o : out std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end timetag_core;
architecture rtl of timetag_core is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component timetag_core_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_timetag_core_in_registers;
regs_o : out t_timetag_core_out_registers);
end component timetag_core_regs;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
......@@ -121,20 +106,23 @@ architecture rtl of timetag_core is
signal acq_stop_tag : t_timetag;
signal acq_end_tag : t_timetag;
signal time_trig : std_logic;
signal time_trig_d : std_logic;
signal time_trig : std_logic;
signal time_trig_d : std_logic;
signal local_pps : std_logic;
signal wr_enabled : std_logic := '0';
signal regin : t_timetag_core_in_registers;
signal regout : t_timetag_core_out_registers;
signal regin : t_timetag_core_master_in;
signal regout : t_timetag_core_master_out;
signal alt_trigin : std_logic;
signal alt_trigin_d : std_logic;
signal alt_trigin_enable : std_logic;
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
begin
-- logic to detect if WR is enabled and timecode is valid
......@@ -143,40 +131,50 @@ begin
------------------------------------------------------------------------------
-- Wishbone interface to UTC core registers
------------------------------------------------------------------------------
cmp_timetag_core_regs : timetag_core_regs
cmp_timetag_wb_slave_adapter_in : wb_slave_adapter
generic map (
g_master_use_struct => TRUE,
g_master_mode => PIPELINED,
g_master_granularity => BYTE,
g_slave_use_struct => TRUE,
g_slave_mode => g_WB_MODE,
g_slave_granularity => g_WB_GRANULARITY)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i => wb_i,
slave_o => wb_o,
master_i => wb_out,
master_o => wb_in);
cmp_timetag_core_regs : entity work.timetag_core_regs
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => open,
regs_i => regin,
regs_o => regout);
regin.seconds_upper_i <= current_time.seconds(39 downto 32);
regin.seconds_lower_i <= current_time.seconds(31 downto 0);
regin.coarse_i <= current_time.coarse;
regin.trig_tag_seconds_upper_i <= trig_tag.seconds(39 downto 32);
regin.trig_tag_seconds_lower_i <= trig_tag.seconds(31 downto 0);
regin.trig_tag_coarse_i <= trig_tag.coarse;
regin.acq_start_tag_seconds_upper_i <= acq_start_tag.seconds(39 downto 32);
regin.acq_start_tag_seconds_lower_i <= acq_start_tag.seconds(31 downto 0);
regin.acq_start_tag_coarse_i <= acq_start_tag.coarse;
regin.acq_stop_tag_seconds_upper_i <= acq_stop_tag.seconds(39 downto 32);
regin.acq_stop_tag_seconds_lower_i <= acq_stop_tag.seconds(31 downto 0);
regin.acq_stop_tag_coarse_i <= acq_stop_tag.coarse;
regin.acq_end_tag_seconds_upper_i <= acq_end_tag.seconds(39 downto 32);
regin.acq_end_tag_seconds_lower_i <= acq_end_tag.seconds(31 downto 0);
regin.acq_end_tag_coarse_i <= acq_end_tag.coarse;
time_trigger.seconds <= regout.time_trig_seconds_upper_o & regout.time_trig_seconds_lower_o;
time_trigger.coarse <= regout.time_trig_coarse_o;
rst_n_i => rst_n_i,
clk_i => clk_i,
wb_i => wb_in,
wb_o => wb_out,
timetag_core_i => regin,
timetag_core_o => regout);
regin.seconds_upper <= current_time.seconds(39 downto 32);
regin.seconds_lower <= current_time.seconds(31 downto 0);
regin.coarse <= current_time.coarse;
regin.trig_tag_seconds_upper <= trig_tag.seconds(39 downto 32);
regin.trig_tag_seconds_lower <= trig_tag.seconds(31 downto 0);
regin.trig_tag_coarse <= trig_tag.coarse;
regin.acq_start_tag_seconds_upper <= acq_start_tag.seconds(39 downto 32);
regin.acq_start_tag_seconds_lower <= acq_start_tag.seconds(31 downto 0);
regin.acq_start_tag_coarse <= acq_start_tag.coarse;
regin.acq_stop_tag_seconds_upper <= acq_stop_tag.seconds(39 downto 32);
regin.acq_stop_tag_seconds_lower <= acq_stop_tag.seconds(31 downto 0);
regin.acq_stop_tag_coarse <= acq_stop_tag.coarse;
regin.acq_end_tag_seconds_upper <= acq_end_tag.seconds(39 downto 32);
regin.acq_end_tag_seconds_lower <= acq_end_tag.seconds(31 downto 0);
regin.acq_end_tag_coarse <= acq_end_tag.coarse;
time_trigger.seconds <= regout.time_trig_seconds_upper & regout.time_trig_seconds_lower;
time_trigger.coarse <= regout.time_trig_coarse;
------------------------------------------------------------------------------
-- UTC seconds counter
......@@ -186,10 +184,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
time_counter.seconds <= (others => '0');
elsif regout.seconds_upper_load_o = '1' then
time_counter.seconds(39 downto 32) <= regout.seconds_upper_o;
elsif regout.seconds_lower_load_o = '1' then
time_counter.seconds(31 downto 0) <= regout.seconds_lower_o;
elsif regout.seconds_upper_wr = '1' then
time_counter.seconds(39 downto 32) <= regout.seconds_upper;
elsif regout.seconds_lower_wr = '1' then
time_counter.seconds(31 downto 0) <= regout.seconds_lower;
elsif local_pps = '1' then
time_counter.seconds <= std_logic_vector(unsigned(current_time.seconds) + 1);
else
......@@ -209,8 +207,8 @@ begin
if rst_n_i = '0' then
time_counter.coarse <= (others => '0');
local_pps <= '0';
elsif regout.coarse_load_o = '1' then
time_counter.coarse <= regout.coarse_o;
elsif regout.coarse_wr = '1' then
time_counter.coarse <= regout.coarse;
local_pps <= '0';
elsif time_counter.coarse = std_logic_vector(c_TAG_COARSE_MAX - 1) then
time_counter.coarse <= (others => '0');
......
files = [
"timetag_core_regs.vhd",
"timetag_core_regs_wbgen2_pkg.vhd",
"timetag_core.vhd",
"timetag_core_pkg.vhd",
]
-------------------------------------------------------------------------------
-- Title : Timetag core package
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : timetag_core_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2019 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2013-07-05 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package timetag_core_pkg is
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type t_timetag is record
seconds : std_logic_vector(39 downto 0);
coarse : std_logic_vector(27 downto 0);
end record t_timetag;
constant c_TAG_COARSE_MAX : unsigned := to_unsigned(125000000, 28);
end timetag_core_pkg;
package body timetag_core_pkg is
end timetag_core_pkg;
This diff is collapsed.
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Time-tagging core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Fri Feb 23 15:43:42 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package timetag_core_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_timetag_core_in_registers is record
seconds_upper_i : std_logic_vector(7 downto 0);
seconds_lower_i : std_logic_vector(31 downto 0);
coarse_i : std_logic_vector(27 downto 0);
trig_tag_seconds_upper_i : std_logic_vector(7 downto 0);
trig_tag_seconds_lower_i : std_logic_vector(31 downto 0);
trig_tag_coarse_i : std_logic_vector(27 downto 0);
acq_start_tag_seconds_upper_i : std_logic_vector(7 downto 0);
acq_start_tag_seconds_lower_i : std_logic_vector(31 downto 0);
acq_start_tag_coarse_i : std_logic_vector(27 downto 0);
acq_stop_tag_seconds_upper_i : std_logic_vector(7 downto 0);
acq_stop_tag_seconds_lower_i : std_logic_vector(31 downto 0);
acq_stop_tag_coarse_i : std_logic_vector(27 downto 0);
acq_end_tag_seconds_upper_i : std_logic_vector(7 downto 0);
acq_end_tag_seconds_lower_i : std_logic_vector(31 downto 0);
acq_end_tag_coarse_i : std_logic_vector(27 downto 0);
end record;
constant c_timetag_core_in_registers_init_value: t_timetag_core_in_registers := (
seconds_upper_i => (others => '0'),
seconds_lower_i => (others => '0'),
coarse_i => (others => '0'),
trig_tag_seconds_upper_i => (others => '0'),
trig_tag_seconds_lower_i => (others => '0'),
trig_tag_coarse_i => (others => '0'),
acq_start_tag_seconds_upper_i => (others => '0'),
acq_start_tag_seconds_lower_i => (others => '0'),
acq_start_tag_coarse_i => (others => '0'),
acq_stop_tag_seconds_upper_i => (others => '0'),
acq_stop_tag_seconds_lower_i => (others => '0'),
acq_stop_tag_coarse_i => (others => '0'),
acq_end_tag_seconds_upper_i => (others => '0'),
acq_end_tag_seconds_lower_i => (others => '0'),
acq_end_tag_coarse_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_timetag_core_out_registers is record
seconds_upper_o : std_logic_vector(7 downto 0);
seconds_upper_load_o : std_logic;
seconds_lower_o : std_logic_vector(31 downto 0);
seconds_lower_load_o : std_logic;
coarse_o : std_logic_vector(27 downto 0);
coarse_load_o : std_logic;
time_trig_seconds_upper_o : std_logic_vector(7 downto 0);
time_trig_seconds_lower_o : std_logic_vector(31 downto 0);
time_trig_coarse_o : std_logic_vector(27 downto 0);
end record;
constant c_timetag_core_out_registers_init_value: t_timetag_core_out_registers := (
seconds_upper_o => (others => '0'),
seconds_upper_load_o => '0',
seconds_lower_o => (others => '0'),
seconds_lower_load_o => '0',
coarse_o => (others => '0'),
coarse_load_o => '0',
time_trig_seconds_upper_o => (others => '0'),
time_trig_seconds_lower_o => (others => '0'),
time_trig_coarse_o => (others => '0')
);
function "or" (left, right: t_timetag_core_in_registers) return t_timetag_core_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body timetag_core_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_timetag_core_in_registers) return t_timetag_core_in_registers is
variable tmp: t_timetag_core_in_registers;
begin
tmp.seconds_upper_i := f_x_to_zero(left.seconds_upper_i) or f_x_to_zero(right.seconds_upper_i);
tmp.seconds_lower_i := f_x_to_zero(left.seconds_lower_i) or f_x_to_zero(right.seconds_lower_i);
tmp.coarse_i := f_x_to_zero(left.coarse_i) or f_x_to_zero(right.coarse_i);
tmp.trig_tag_seconds_upper_i := f_x_to_zero(left.trig_tag_seconds_upper_i) or f_x_to_zero(right.trig_tag_seconds_upper_i);
tmp.trig_tag_seconds_lower_i := f_x_to_zero(left.trig_tag_seconds_lower_i) or f_x_to_zero(right.trig_tag_seconds_lower_i);
tmp.trig_tag_coarse_i := f_x_to_zero(left.trig_tag_coarse_i) or f_x_to_zero(right.trig_tag_coarse_i);
tmp.acq_start_tag_seconds_upper_i := f_x_to_zero(left.acq_start_tag_seconds_upper_i) or f_x_to_zero(right.acq_start_tag_seconds_upper_i);
tmp.acq_start_tag_seconds_lower_i := f_x_to_zero(left.acq_start_tag_seconds_lower_i) or f_x_to_zero(right.acq_start_tag_seconds_lower_i);
tmp.acq_start_tag_coarse_i := f_x_to_zero(left.acq_start_tag_coarse_i) or f_x_to_zero(right.acq_start_tag_coarse_i);
tmp.acq_stop_tag_seconds_upper_i := f_x_to_zero(left.acq_stop_tag_seconds_upper_i) or f_x_to_zero(right.acq_stop_tag_seconds_upper_i);
tmp.acq_stop_tag_seconds_lower_i := f_x_to_zero(left.acq_stop_tag_seconds_lower_i) or f_x_to_zero(right.acq_stop_tag_seconds_lower_i);
tmp.acq_stop_tag_coarse_i := f_x_to_zero(left.acq_stop_tag_coarse_i) or f_x_to_zero(right.acq_stop_tag_coarse_i);
tmp.acq_end_tag_seconds_upper_i := f_x_to_zero(left.acq_end_tag_seconds_upper_i) or f_x_to_zero(right.acq_end_tag_seconds_upper_i);
tmp.acq_end_tag_seconds_lower_i := f_x_to_zero(left.acq_end_tag_seconds_lower_i) or f_x_to_zero(right.acq_end_tag_seconds_lower_i);
tmp.acq_end_tag_coarse_i := f_x_to_zero(left.acq_end_tag_coarse_i) or f_x_to_zero(right.acq_end_tag_coarse_i);
return tmp;
end function;
end package body;
WBGEN2=$(shell which wbgen2)
RTL=../
TEX=../../../../doc/manual/
SIM=../../../testbench/include/
timetag_core_regs:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h -K $(SIM)$@.v $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
/*
Register definitions for slave core: Time-tagging core registers
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Fri Feb 23 15:43:42 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB
#define __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Timetag seconds register (upper) */
/* definitions for register: Timetag seconds register (lower) */
/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
/* definitions for register: Time trigger seconds register (upper) */
/* definitions for register: Time trigger seconds register (lower) */
/* definitions for register: Time trigger coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag seconds register (upper) */
/* definitions for register: Trigger time-tag seconds register (lower) */
/* definitions for register: Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition start time-tag seconds register (upper) */
/* definitions for register: Acquisition start time-tag seconds register (lower) */
/* definitions for register: Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition stop time-tag seconds register (upper) */
/* definitions for register: Acquisition stop time-tag seconds register (lower) */
/* definitions for register: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition end time-tag seconds register (upper) */
/* definitions for register: Acquisition end time-tag seconds register (lower) */
/* definitions for register: Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
PACKED struct TIMETAG_CORE_WB {
/* [0x0]: REG Timetag seconds register (upper) */
uint32_t SECONDS_UPPER;
/* [0x4]: REG Timetag seconds register (lower) */
uint32_t SECONDS_LOWER;
/* [0x8]: REG Timetag coarse time register, system clock ticks (125MHz) */
uint32_t COARSE;
/* [0xc]: REG Time trigger seconds register (upper) */
uint32_t TIME_TRIG_SECONDS_UPPER;
/* [0x10]: REG Time trigger seconds register (lower) */
uint32_t TIME_TRIG_SECONDS_LOWER;
/* [0x14]: REG Time trigger coarse time register, system clock ticks (125MHz) */
uint32_t TIME_TRIG_COARSE;
/* [0x18]: REG Trigger time-tag seconds register (upper) */
uint32_t TRIG_TAG_SECONDS_UPPER;
/* [0x1c]: REG Trigger time-tag seconds register (lower) */
uint32_t TRIG_TAG_SECONDS_LOWER;
/* [0x20]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t TRIG_TAG_COARSE;
/* [0x24]: REG Acquisition start time-tag seconds register (upper) */
uint32_t ACQ_START_TAG_SECONDS_UPPER;
/* [0x28]: REG Acquisition start time-tag seconds register (lower) */
uint32_t ACQ_START_TAG_SECONDS_LOWER;
/* [0x2c]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_START_TAG_COARSE;
/* [0x30]: REG Acquisition stop time-tag seconds register (upper) */
uint32_t ACQ_STOP_TAG_SECONDS_UPPER;
/* [0x34]: REG Acquisition stop time-tag seconds register (lower) */
uint32_t ACQ_STOP_TAG_SECONDS_LOWER;
/* [0x38]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_STOP_TAG_COARSE;
/* [0x3c]: REG Acquisition end time-tag seconds register (upper) */
uint32_t ACQ_END_TAG_SECONDS_UPPER;
/* [0x40]: REG Acquisition end time-tag seconds register (lower) */
uint32_t ACQ_END_TAG_SECONDS_LOWER;
/* [0x44]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_END_TAG_COARSE;
};
#endif
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peripheral {
name = "Time-tagging core registers";
description = "Wishbone slave for registers related to time-tagging core";
hdl_entity = "timetag_core_regs";
prefix = "timetag_core";
reg {
name = "Timetag seconds register (upper)";
description = "8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_upper";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag seconds register (lower)";
description = "32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_lower";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag coarse time register, system clock ticks (125MHz)";
description = "Coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "coarse";
field {
name = "Timetag coarse time";
type = SLV;
load = LOAD_EXT;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};