Migrate ADC CSR to Cheby

e084c507 · Dimitris Lampridis · 9685afca · e084c507 · e084c507 · e084c507
Commit e084c507 authored Jul 30, 2019 by Dimitris Lampridis
26 changed files
--- a/doc/manual/fmc_adc_100Ms_csr.adoc
+++ b/doc/manual/fmc_adc_100Ms_csr.adoc
--- a/doc/manual/fmc_adc_alt_trigin.adoc
+++ b/doc/manual/fmc_adc_alt_trigin.adoc
+== Memory map summary
+FMC ADC alt trigger out registers
+
+|===
+|HW address | Type | Name | HDL name
+
+|0x00
+|REG
+|version
+|version
+
+|0x04
+|REG
+|ctrl
+|ctrl
+
+|0x08
+|REG
+|seconds
+|seconds
+
+|0x10
+|REG
+|cycles
+|cycles
+|===
+
+== Registers description
+=== version
+[horizontal]
+HDL name:: version
+address:: 0x0
+block offset:: 0x0
+access mode:: ro
+
+Core version
+
+[cols="8*^"]
+|===
+
+| 31
+| 30
+| 29
+| 28
+| 27
+| 26
+| 25
+| 24
+
+8+s| version[31:24]
+
+| 23
+| 22
+| 21
+| 20
+| 19
+| 18
+| 17
+| 16
+
+8+s| version[23:16]
+
+| 15
+| 14
+| 13
+| 12
+| 11
+| 10
+| 9
+| 8
+
+8+s| version[15:8]
+
+| 7
+| 6
+| 5
+| 4
+| 3
+| 2
+| 1
+| 0
+
+8+s| version[7:0]
+|===
+=== ctrl
+[horizontal]
+HDL name:: ctrl
+address:: 0x4
+block offset:: 0x4
+access mode:: rw
+
+Control register
+
+[cols="8*^"]
+|===
+
+| 31
+| 30
+| 29
+| 28
+| 27
+| 26
+| 25
+| 24
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+
+| 23
+| 22
+| 21
+| 20
+| 19
+| 18
+| 17
+| 16
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+
+| 15
+| 14
+| 13
+| 12
+| 11
+| 10
+| 9
+| 8
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+
+| 7
+| 6
+| 5
+| 4
+| 3
+| 2
+| 1
+| 0
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+s| enable
+|===
+
+enable:: Enable trigger, cleared when triggered
+
+=== seconds
+[horizontal]
+HDL name:: seconds
+address:: 0x8
+block offset:: 0x8
+access mode:: rw
+
+Time (seconds) to trigger
+
+[cols="8*^"]
+|===
+
+| 63
+| 62
+| 61
+| 60
+| 59
+| 58
+| 57
+| 56
+
+8+s| seconds[63:56]
+
+| 55
+| 54
+| 53
+| 52
+| 51
+| 50
+| 49
+| 48
+
+8+s| seconds[55:48]
+
+| 47
+| 46
+| 45
+| 44
+| 43
+| 42
+| 41
+| 40
+
+8+s| seconds[47:40]
+
+| 39
+| 38
+| 37
+| 36
+| 35
+| 34
+| 33
+| 32
+
+8+s| seconds[39:32]
+
+| 31
+| 30
+| 29
+| 28
+| 27
+| 26
+| 25
+| 24
+
+8+s| seconds[31:24]
+
+| 23
+| 22
+| 21
+| 20
+| 19
+| 18
+| 17
+| 16
+
+8+s| seconds[23:16]
+
+| 15
+| 14
+| 13
+| 12
+| 11
+| 10
+| 9
+| 8
+
+8+s| seconds[15:8]
+
+| 7
+| 6
+| 5
+| 4
+| 3
+| 2
+| 1
+| 0
+
+8+s| seconds[7:0]
+|===
+=== cycles
+[horizontal]
+HDL name:: cycles
+address:: 0x10
+block offset:: 0x10
+access mode:: rw
+
+Time (cycles) to trigger
+
+[cols="8*^"]
+|===
+
+| 31
+| 30
+| 29
+| 28
+| 27
+| 26
+| 25
+| 24
+
+8+s| cycles[31:24]
+
+| 23
+| 22
+| 21
+| 20
+| 19
+| 18
+| 17
+| 16
+
+8+s| cycles[23:16]
+
+| 15
+| 14
+| 13
+| 12
+| 11
+| 10
+| 9
+| 8
+
+8+s| cycles[15:8]
+
+| 7
+| 6
+| 5
+| 4
+| 3
+| 2
+| 1
+| 0
+
+8+s| cycles[7:0]
+|===
--- a/doc/manual/fmc_adc_alt_trigout.adoc
+++ b/doc/manual/fmc_adc_alt_trigout.adoc
+== Memory map summary
+FMC ADC alt trigger out registers
+
+|===
+|HW address | Type | Name | HDL name
+
+|0x00
+|REG
+|status
+|status
+
+|0x08
+|REG
+|ts_mask_sec
+|ts_mask_sec
+
+|0x10
+|REG
+|ts_cycles
+|ts_cycles
+|===
+
+== Registers description
+=== status
+[horizontal]
+HDL name:: status
+address:: 0x0
+block offset:: 0x0
+access mode:: ro
+
+Status register
+
+[cols="8*^"]
+|===
+
+| 31
+| 30
+| 29
+| 28
+| 27
+| 26
+| 25
+| 24
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+
+| 23
+| 22
+| 21
+| 20
+| 19
+| 18
+| 17
+| 16
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+
+| 15
+| 14
+| 13
+| 12
+| 11
+| 10
+| 9
+| 8
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+s| ts_present
+
+| 7
+| 6
+| 5
+| 4
+| 3
+| 2
+| 1
+| 0
+
+| -
+| -
+| -
+| -
+| -
+s| wr_valid
+s| wr_link
+s| wr_enable
+|===
+
+wr_enable:: Set when WR is enabled
+wr_link:: WR link status
+wr_valid:: Set when WR time is valid
+ts_present:: Set when the timestamp fifo is not empty
+
+=== ts_mask_sec
+[horizontal]
+HDL name:: ts_mask_sec
+address:: 0x8
+block offset:: 0x8
+access mode:: ro
+
+Time (seconds) of the last event
+
+[cols="8*^"]
+|===
+
+| 63
+| 62
+| 61
+| 60
+| 59
+| 58
+| 57
+| 56
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+s| ext_mask
+
+| 55
+| 54
+| 53
+| 52
+| 51
+| 50
+| 49
+| 48
+
+| -
+| -
+| -
+| -
+s| ch4_mask
+s| ch3_mask
+s| ch2_mask
+s| ch1_mask
+
+| 47
+| 46
+| 45
+| 44
+| 43
+| 42
+| 41
+| 40
+
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+| -
+
+| 39
+| 38
+| 37
+| 36
+| 35
+| 34
+| 33
+| 32
+
+8+s| ts_sec[39:32]
+
+| 31
+| 30
+| 29
+| 28
+| 27
+| 26
+| 25
+| 24
+
+8+s| ts_sec[31:24]
+
+| 23
+| 22
+| 21
+| 20
+| 19
+| 18
+| 17
+| 16
+
+8+s| ts_sec[23:16]
+
+| 15
+| 14
+| 13
+| 12
+| 11
+| 10
+| 9
+| 8
+
+8+s| ts_sec[15:8]
+
+| 7
+| 6
+| 5
+| 4
+| 3
+| 2
+| 1
+| 0
+
+8+s| ts_sec[7:0]
+|===
+
+ts_sec:: Seconds part of the timestamp
+ch1_mask:: Set if channel 1 triggered
+ch2_mask:: Set if channel 2 triggered
+ch3_mask:: Set if channel 3 triggered
+ch4_mask:: Set if channel 4 triggered
+ext_mask:: Set if external trigger
+
+=== ts_cycles
+[horizontal]
+HDL name:: ts_cycles
+address:: 0x10
+block offset:: 0x10
+access mode:: ro
+
+Cycles part of timestamp fifo.
+
+[cols="8*^"]
+|===
+
+| 31
+| 30
+| 29
+| 28
+| 27
+| 26
+| 25
+| 24
+
+| -
+| -
+| -
+| -
+4+s| cycles[27:24]
+
+| 23
+| 22
+| 21
+| 20
+| 19
+| 18
+| 17
+| 16
+
+8+s| cycles[23:16]
+
+| 15
+| 14
+| 13
+| 12
+| 11
+| 10
+| 9
+| 8
+
+8+s| cycles[15:8]
+
+| 7
+| 6
+| 5
+| 4
+| 3
+| 2
+| 1
+| 0
+
+8+s| cycles[7:0]
+|===
+
+cycles:: Cycles
+
--- a/general-cores @ eaacde90
+++ b/general-cores @ eaacde90
-Subproject commit 28cd756047ce9f85cf7c134367c7439f1189114d
+Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3
--- a/hdl/rtl/Makefile
+++ b/hdl/rtl/Makefile
+SIM   =../testbench/include
+DOC   =../../doc/manual
+
+SOURCES = $(wildcard *.cheby)
+TARGETS = $(SOURCES:.cheby=.vhd)
+
+all: $(TARGETS)
+
+.PHONY: $(TARGETS)
+
+$(TARGETS): %.vhd : %.cheby
+	@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
+	@cheby -i $< --gen-hdl=$@
+	@cheby -i $< --doc=md --gen-doc=$(DOC)/$(@:.vhd=.adoc)
+	@cheby -i $< --gen-consts=$(SIM)/$(@:.vhd=.v)
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
@@ -4,7 +4,6 @@ files = [
    "fmc_adc_100Ms_core.vhd",
    "fmc_adc_100Ms_core_pkg.vhd",
    "fmc_adc_100Ms_csr.vhd",
-    "fmc_adc_100Ms_csr_wbgen2_pkg.vhd",
    "fmc_adc_alt_trigin.vhd",
    "fmc_adc_alt_trigout.vhd",
    "fmc_adc_eic.vhd",

--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
--- a/hdl/rtl/fmc_adc_100Ms_csr.cheby
+++ b/hdl/rtl/fmc_adc_100Ms_csr.cheby
--- a/hdl/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_csr.vhd
--- a/hdl/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
--- a/hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby
+++ b/hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby
 memory-map:
  bus: wb-32-be
  name: alt_trigin
+  description: FMC ADC alt trigger out registers
  x-hdl:
    busgroup: True
  children:

--- a/hdl/rtl/fmc_adc_alt_trigin.vhd
+++ b/hdl/rtl/fmc_adc_alt_trigin.vhd
--- a/hdl/rtl/wb_gen/fmc_adc_alt_trigout.cheby
+++ b/hdl/rtl/wb_gen/fmc_adc_alt_trigout.cheby
 memory-map:
  bus: wb-32-be
  name: alt_trigout
+  description: FMC ADC alt trigger out registers
  x-hdl:
    busgroup: True
    reg_prefix: False

--- a/hdl/rtl/fmc_adc_alt_trigout.vhd
+++ b/hdl/rtl/fmc_adc_alt_trigout.vhd
--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -163,12 +163,12 @@ architecture rtl of fmc_adc_mezzanine is
    wbd_width     => x"4",                        -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
-      addr_last   => x"00000000000003FF",
+      addr_last   => x"00000000000001FF",
      product     => (
        vendor_id => x"000000000000CE42",         -- CERN
        device_id => x"00000608",
-        version   => x"00000001",
-        date      => x"20121116",
+        version   => x"00000002",
+        date      => x"20190730",
        name      => "WB-FMC-ADC-Core    ")));

  constant c_wb_timetag_sdb : t_sdb_device := (

--- a/hdl/rtl/wb_gen/Makefile
+++ b/hdl/rtl/wb_gen/Makefile
 WBGEN2=$(shell which wbgen2)
-CHEBY=cheby
 RTL=../
 SIM=../../testbench/include/
 TEX=../../../doc/manual/

-all: fmc_adc_100Ms_csr fmc_adc_eic fmc_adc_alt_trigin fmc_adc_alt_trigout
-
-fmc_adc_100Ms_csr:
-	$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h  -K $(SIM)$@.v $@.wb
-	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
+all: fmc_adc_eic

 fmc_adc_eic:
 	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
 	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
-
-fmc_adc_alt_trigin:
-	$(CHEBY) --gen-hdl=$(RTL)/$@.vhd --gen-doc=$@.html --gen-c=$@.h --gen-consts=$(SIM)/$@.v -i $@.cheby
-
-fmc_adc_alt_trigout:
-	$(CHEBY) --gen-hdl=$(RTL)/$@.vhd --gen-doc=$@.html --gen-c=$@.h --gen-consts=$(SIM)/$@.v -i $@.cheby
--- a/hdl/rtl/wb_gen/fmc_adc_100Ms_csr.h
+++ b/hdl/rtl/wb_gen/fmc_adc_100Ms_csr.h
--- a/hdl/rtl/wb_gen/fmc_adc_100Ms_csr.htm
+++ b/hdl/rtl/wb_gen/fmc_adc_100Ms_csr.htm
--- a/hdl/rtl/wb_gen/fmc_adc_100Ms_csr.wb
+++ b/hdl/rtl/wb_gen/fmc_adc_100Ms_csr.wb
--- a/hdl/rtl/wb_gen/fmc_adc_alt_trigin.h
+++ b/hdl/rtl/wb_gen/fmc_adc_alt_trigin.h
--- a/hdl/rtl/wb_gen/fmc_adc_alt_trigin.html
+++ b/hdl/rtl/wb_gen/fmc_adc_alt_trigin.html
--- a/hdl/rtl/wb_gen/fmc_adc_alt_trigout.h
+++ b/hdl/rtl/wb_gen/fmc_adc_alt_trigout.h
--- a/hdl/rtl/wb_gen/fmc_adc_alt_trigout.html
+++ b/hdl/rtl/wb_gen/fmc_adc_alt_trigout.html
--- a/hdl/testbench/fmc_adc_mezzanine/main.sv
+++ b/hdl/testbench/fmc_adc_mezzanine/main.sv
--- a/hdl/testbench/include/fmc_adc_100Ms_csr.v
+++ b/hdl/testbench/include/fmc_adc_100Ms_csr.v
--- a/hdl/testbench/svec_ref_design/main.sv
+++ b/hdl/testbench/svec_ref_design/main.sv