Make sampling clock available as fmc_adc_mezzanine port

342e311b · Tomasz Wlostowski · 21c53031 · 342e311b · 342e311b
Commit 342e311b authored Apr 03, 2023 by Tomasz Wlostowski
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Showing with 11 additions and 2 deletions

fmc_adc_100Ms_core.vhd hdl/rtl/fmc_adc_100Ms_core.vhd +4 -0

fmc_adc_mezzanine.vhd hdl/rtl/fmc_adc_mezzanine.vhd +7 -2

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--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
@@ -96,6 +96,8 @@ entity fmc_adc_100Ms_core is
    adc_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
    adc_outb_n_i : in std_logic_vector(3 downto 0);

+    adc_fs_clk_o : out std_logic; -- FMC sampling clock out for WR SoftPLL
+    
    gpio_dac_clr_n_o : out std_logic;             -- offset DACs clear (active low)
    gpio_led_acq_o   : out std_logic;             -- Mezzanine front panel power LED (PWR)
    gpio_led_trig_o  : out std_logic;             -- Mezzanine front panel trigger LED (TRIG)
@@ -1826,4 +1828,6 @@ begin
    trigout_fifo_din(t_trigout_data_coarse'range)   <= trigger_tag_i.coarse;
    trigout_fifo_din(t_trigout_data_channels'range) <= trigout_triggers;
  end block b_trigout;
+
+  adc_fs_clk_o <= fs_clk;
 end rtl;
--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -88,7 +88,8 @@ entity fmc_adc_mezzanine is
    adc_outa_n_i : in std_logic_vector(3 downto 0);
    adc_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
    adc_outb_n_i : in std_logic_vector(3 downto 0);
-
+    adc_fs_clk_o : out std_logic;
+    
    gpio_dac_clr_n_o : out std_logic;             -- offset DACs clear (active low)
    gpio_led_acq_o   : out std_logic;             -- Mezzanine front panel power LED (PWR)
    gpio_led_trig_o  : out std_logic;             -- Mezzanine front panel trigger LED (TRIG)
@@ -98,6 +99,8 @@ entity fmc_adc_mezzanine is
    gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
    gpio_si570_oe_o  : out std_logic;             -- Si570 (programmable oscillator) output enable

+
+    
    spi_din_i       : in  std_logic;              -- SPI data from FMC
    spi_dout_o      : out std_logic;              -- SPI data to FMC
    spi_sck_o       : out std_logic;              -- SPI clock
@@ -363,7 +366,9 @@ begin
      gpio_ssr_ch2_o   => gpio_ssr_ch2_o,
      gpio_ssr_ch3_o   => gpio_ssr_ch3_o,
      gpio_ssr_ch4_o   => gpio_ssr_ch4_o,
-      gpio_si570_oe_o  => gpio_si570_oe_o);
+      gpio_si570_oe_o  => gpio_si570_oe_o,
+      adc_fs_clk_o => adc_fs_clk_o
+      );

  ------------------------------------------------------------------------------
  -- Mezzanine 1-wire master