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FMC ADC 100M 14b 4cha
Commit 13aaea4b authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[svec] migrate design to the Convention

parent f54f430a
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.gitmodules
View file @ 13aaea4b
......@@ -16,3 +16,6 @@
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby 0 → 100644
View file @ 13aaea4b
memory-map:
name: spec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x8000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
address: 0x2000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: fmc1_adc_mezzanine
address: 0x4000
description: FMC ADC Mezzanine slot 1
filename: fmc_adc_mezzanine_mmap.cheby
- submap:
name: fmc2_adc_mezzanine
address: 0x6000
description: FMC ADC Mezzanine slot 2
filename: fmc_adc_mezzanine_mmap.cheby
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd 0 → 100644
View file @ 13aaea4b
-- Do not edit; this file was generated by Cheby using these options:
-- -i svec_ref_fmc_adc_100Ms_mmap.cheby --gen-hdl=svec_ref_fmc_adc_100Ms_mmap.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_ref_fmc_adc_100m_mmap is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the application metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 1
fmc1_adc_mezzanine_i : in t_wishbone_master_in;
fmc1_adc_mezzanine_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 2
fmc2_adc_mezzanine_i : in t_wishbone_master_in;
fmc2_adc_mezzanine_o : out t_wishbone_master_out
);
end spec_ref_fmc_adc_100m_mmap;
architecture syn of spec_ref_fmc_adc_100m_mmap is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fmc1_adc_mezzanine_re : std_logic;
signal fmc1_adc_mezzanine_wt : std_logic;
signal fmc1_adc_mezzanine_rt : std_logic;
signal fmc1_adc_mezzanine_tr : std_logic;
signal fmc1_adc_mezzanine_wack : std_logic;
signal fmc1_adc_mezzanine_rack : std_logic;
signal fmc2_adc_mezzanine_re : std_logic;
signal fmc2_adc_mezzanine_wt : std_logic;
signal fmc2_adc_mezzanine_rt : std_logic;
signal fmc2_adc_mezzanine_tr : std_logic;
signal fmc2_adc_mezzanine_wack : std_logic;
signal fmc2_adc_mezzanine_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- Assignments for submap metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & wb_i.adr(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= (others => '1');
metadata_o.we <= metadata_wt;
metadata_o.dat <= wb_i.dat;
-- Assignments for submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_tr <= fmc1_adc_mezzanine_wt or fmc1_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc1_adc_mezzanine_rt <= '0';
else
fmc1_adc_mezzanine_rt <= (fmc1_adc_mezzanine_rt or fmc1_adc_mezzanine_re) and not fmc1_adc_mezzanine_rack;
end if;
end if;
end process;
fmc1_adc_mezzanine_o.cyc <= fmc1_adc_mezzanine_tr;
fmc1_adc_mezzanine_o.stb <= fmc1_adc_mezzanine_tr;
fmc1_adc_mezzanine_wack <= fmc1_adc_mezzanine_i.ack and fmc1_adc_mezzanine_wt;
fmc1_adc_mezzanine_rack <= fmc1_adc_mezzanine_i.ack and fmc1_adc_mezzanine_rt;
fmc1_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc1_adc_mezzanine_o.sel <= (others => '1');
fmc1_adc_mezzanine_o.we <= fmc1_adc_mezzanine_wt;
fmc1_adc_mezzanine_o.dat <= wb_i.dat;
-- Assignments for submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_tr <= fmc2_adc_mezzanine_wt or fmc2_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc2_adc_mezzanine_rt <= '0';
else
fmc2_adc_mezzanine_rt <= (fmc2_adc_mezzanine_rt or fmc2_adc_mezzanine_re) and not fmc2_adc_mezzanine_rack;
end if;
end if;
end process;
fmc2_adc_mezzanine_o.cyc <= fmc2_adc_mezzanine_tr;
fmc2_adc_mezzanine_o.stb <= fmc2_adc_mezzanine_tr;
fmc2_adc_mezzanine_wack <= fmc2_adc_mezzanine_i.ack and fmc2_adc_mezzanine_wt;
fmc2_adc_mezzanine_rack <= fmc2_adc_mezzanine_i.ack and fmc2_adc_mezzanine_rt;
fmc2_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc2_adc_mezzanine_o.sel <= (others => '1');
fmc2_adc_mezzanine_o.we <= fmc2_adc_mezzanine_wt;
fmc2_adc_mezzanine_o.dat <= wb_i.dat;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wt <= '0';
fmc1_adc_mezzanine_wt <= '0';
fmc2_adc_mezzanine_wt <= '0';
else
wr_ack_int <= '0';
metadata_wt <= '0';
fmc1_adc_mezzanine_wt <= '0';
fmc2_adc_mezzanine_wt <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_wt <= (metadata_wt or wr_int) and not metadata_wack;
wr_ack_int <= metadata_wack;
when "10" =>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_wt <= (fmc1_adc_mezzanine_wt or wr_int) and not fmc1_adc_mezzanine_wack;
wr_ack_int <= fmc1_adc_mezzanine_wack;
when "11" =>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_wt <= (fmc2_adc_mezzanine_wt or wr_int) and not fmc2_adc_mezzanine_wack;
wr_ack_int <= fmc2_adc_mezzanine_wack;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(14 downto 13) is
when "01" =>
when "10" =>
when "11" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_i.dat, metadata_rack, metadata_rt, rd_int, fmc1_adc_mezzanine_i.dat, fmc1_adc_mezzanine_rack, fmc1_adc_mezzanine_rt, rd_int, fmc2_adc_mezzanine_i.dat, fmc2_adc_mezzanine_rack, fmc2_adc_mezzanine_rt) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
metadata_re <= '0';
fmc1_adc_mezzanine_re <= '0';
fmc2_adc_mezzanine_re <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_re <= rd_int;
wb_o.dat <= metadata_i.dat;
rd_ack_int <= metadata_rack;
when "10" =>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_re <= rd_int;
wb_o.dat <= fmc1_adc_mezzanine_i.dat;
rd_ack_int <= fmc1_adc_mezzanine_rack;
when "11" =>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_re <= rd_int;
wb_o.dat <= fmc2_adc_mezzanine_i.dat;
rd_ack_int <= fmc2_adc_mezzanine_rack;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
general-cores @ 75d51c0b
Subproject commit be61ce73a43d0231e8edc2f12133b918e3d1c9e4
Subproject commit 75d51c0b92015b48b176374f9a387b2d25fa8198
svec @ 8aa8d699
Subproject commit 8aa8d699f30c3ed1d02e3aa96c00492fdb0e2051
vme64x-core @ 6abee52c
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
Subproject commit 6abee52c1b5f3c2a40e202eb9f5890c05e0d7f66
hdl/syn/svec_ref_design_wr/Manifest.py
View file @ 13aaea4b
......@@ -9,29 +9,30 @@ syn_top = "svec_ref_fmc_adc_100Ms"
syn_project = syn_top + "_wr.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
files = [
syn_top + "_wr.ucf",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec_ref_design"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
],
}
fetchto="../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
svec_base_ucf = ['wr', 'ddr4', 'ddr5', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @ 13aaea4b
......@@ -2,424 +2,6 @@
# IO Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[*]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[*]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DDR Memory
#----------------------------------------
# DDR0 (bank 4)
NET "ddr_rzq_b[0]" LOC = L7;
NET "ddr_we_n_o[0]" LOC = F4;
NET "ddr_udqs_p_b[0]" LOC = K2;
NET "ddr_udqs_n_b[0]" LOC = K1;
NET "ddr_udm_o[0]" LOC = K4;
NET "ddr_reset_n_o[0]" LOC = G5;
NET "ddr_ras_n_o[0]" LOC = C1;
NET "ddr_odt_o[0]" LOC = E4;
NET "ddr_ldqs_p_b[0]" LOC = J5;
NET "ddr_ldqs_n_b[0]" LOC = J4;
NET "ddr_ldm_o[0]" LOC = K3;
NET "ddr_cke_o[0]" LOC = C4;
NET "ddr_ck_p_o[0]" LOC = E3;
NET "ddr_ck_n_o[0]" LOC = E1;
NET "ddr_cas_n_o[0]" LOC = B1;
NET "ddr_dq_b[15]" LOC = M1;
NET "ddr_dq_b[14]" LOC = M2;
NET "ddr_dq_b[13]" LOC = L1;
NET "ddr_dq_b[12]" LOC = L3;
NET "ddr_dq_b[11]" LOC = L4;
NET "ddr_dq_b[10]" LOC = L5;
NET "ddr_dq_b[9]" LOC = M3;
NET "ddr_dq_b[8]" LOC = M4;
NET "ddr_dq_b[7]" LOC = H1;
NET "ddr_dq_b[6]" LOC = H2;
NET "ddr_dq_b[5]" LOC = G1;
NET "ddr_dq_b[4]" LOC = G3;
NET "ddr_dq_b[3]" LOC = J1;
NET "ddr_dq_b[2]" LOC = J3;
NET "ddr_dq_b[1]" LOC = H3;
NET "ddr_dq_b[0]" LOC = H4;
NET "ddr_ba_o[2]" LOC = F3;
NET "ddr_ba_o[1]" LOC = D1;
NET "ddr_ba_o[0]" LOC = D2;
NET "ddr_a_o[13]" LOC = B5;
NET "ddr_a_o[12]" LOC = A4;
NET "ddr_a_o[11]" LOC = G4;
NET "ddr_a_o[10]" LOC = D5;
NET "ddr_a_o[9]" LOC = A2;
NET "ddr_a_o[8]" LOC = B2;
NET "ddr_a_o[7]" LOC = B3;
NET "ddr_a_o[6]" LOC = F1;
NET "ddr_a_o[5]" LOC = F2;
NET "ddr_a_o[4]" LOC = C5;
NET "ddr_a_o[3]" LOC = E5;
NET "ddr_a_o[2]" LOC = A3;
NET "ddr_a_o[1]" LOC = D3;
NET "ddr_a_o[0]" LOC = D4;
# DDR1 (bank 5)
NET "ddr_rzq_b[1]" LOC = G25;
NET "ddr_we_n_o[1]" LOC = E26;
NET "ddr_udqs_p_b[1]" LOC = K28;
NET "ddr_udqs_n_b[1]" LOC = K30;
NET "ddr_udm_o[1]" LOC = J27;
NET "ddr_reset_n_o[1]" LOC = C26;
NET "ddr_ras_n_o[1]" LOC = K26;
NET "ddr_odt_o[1]" LOC = E30;
NET "ddr_ldqs_p_b[1]" LOC = J29;
NET "ddr_ldqs_n_b[1]" LOC = J30;
NET "ddr_ldm_o[1]" LOC = J28;
NET "ddr_cke_o[1]" LOC = B29;
NET "ddr_ck_p_o[1]" LOC = E27;
NET "ddr_ck_n_o[1]" LOC = E28;
NET "ddr_cas_n_o[1]" LOC = K27;
NET "ddr_dq_b[31]" LOC = M30;
NET "ddr_dq_b[30]" LOC = M28;
NET "ddr_dq_b[29]" LOC = M27;
NET "ddr_dq_b[28]" LOC = M26;
NET "ddr_dq_b[27]" LOC = L30;
NET "ddr_dq_b[26]" LOC = L29;
NET "ddr_dq_b[25]" LOC = L28;
NET "ddr_dq_b[24]" LOC = L27;
NET "ddr_dq_b[23]" LOC = F30;
NET "ddr_dq_b[22]" LOC = F28;
NET "ddr_dq_b[21]" LOC = G28;
NET "ddr_dq_b[20]" LOC = G27;
NET "ddr_dq_b[19]" LOC = G30;
NET "ddr_dq_b[18]" LOC = G29;
NET "ddr_dq_b[17]" LOC = H30;
NET "ddr_dq_b[16]" LOC = H28;
NET "ddr_ba_o[5]" LOC = D26;
NET "ddr_ba_o[4]" LOC = C27;
NET "ddr_ba_o[3]" LOC = D27;
NET "ddr_a_o[27]" LOC = A28;
NET "ddr_a_o[26]" LOC = B30;
NET "ddr_a_o[25]" LOC = A26;
NET "ddr_a_o[24]" LOC = F26;
NET "ddr_a_o[23]" LOC = A27;
NET "ddr_a_o[22]" LOC = B27;
NET "ddr_a_o[21]" LOC = C29;
NET "ddr_a_o[20]" LOC = H27;
NET "ddr_a_o[19]" LOC = H26;
NET "ddr_a_o[18]" LOC = F27;
NET "ddr_a_o[17]" LOC = E29;
NET "ddr_a_o[16]" LOC = C30;
NET "ddr_a_o[15]" LOC = D30;
NET "ddr_a_o[14]" LOC = D28;
# DDR IO standards and terminations
NET "ddr_udqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_n_b[*]" IN_TERM = NONE;
NET "ddr_udqs_p_b[*]" IN_TERM = NONE;
NET "ddr_udqs_n_b[*]" IN_TERM = NONE;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AG27;
NET "spi_sclk_o" LOC = AG26;
NET "spi_mosi_o" LOC = AH26;
NET "spi_miso_i" LOC = AH27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[*]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Front panel IOs
#----------------------------------------
NET "fp_gpio1_o" LOC = T28;
NET "fp_gpio2_o" LOC = R30;
NET "fp_gpio3_o" LOC = V27;
NET "fp_gpio4_o" LOC = U29;
NET "fp_gpio1_a2b_o" LOC = T30;
NET "fp_gpio2_a2b_o" LOC = R29;
NET "fp_gpio34_a2b_o" LOC = V28;
NET "fp_term_en_o[1]" LOC = AB1;
NET "fp_term_en_o[2]" LOC = W5;
NET "fp_term_en_o[3]" LOC = W4;
NET "fp_term_en_o[4]" LOC = V4;
NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio3_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio4_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[4]" LOC = AF17;
NET "pcbrev_i[3]" LOC = AE17;
NET "pcbrev_i[2]" LOC = AD18;
NET "pcbrev_i[1]" LOC = AE20;
NET "pcbrev_i[0]" LOC = AD20;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
NET "carrier_scl_b" LOC = AC29;
NET "carrier_sda_b" LOC = AA30;
NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slots management
#----------------------------------------
NET "fmc_prsnt_m2c_n_i[0]" LOC = N30;
NET "fmc_prsnt_m2c_n_i[1]" LOC = AE29;
NET "fmc_scl_b[0]" LOC = P28;
NET "fmc_scl_b[1]" LOC = W29;
NET "fmc_sda_b[0]" LOC = P30;
NET "fmc_sda_b[1]" LOC = V30;
NET "fmc_prsnt_m2c_n_i[*]" IOSTANDARD = "LVCMOS33";
NET "fmc_scl_b[*]" IOSTANDARD = "LVCMOS33";
NET "fmc_sda_b[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slots
#----------------------------------------
......@@ -577,136 +159,53 @@ NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#===============================================================================
# Timing Constraints
# Timing constraints and exceptions
#===============================================================================
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
#----------------------------------------
# Clocks
# IOB exceptions
#----------------------------------------
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_ref;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_ref;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "adc_dco_p_i[0]" TNM_NET = adc0_dco;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco;
TIMESPEC TS_adc0_dco = PERIOD "adc0_dco" 2.5 ns HIGH 50%;
NET "adc_dco_p_i[1]" TNM_NET = adc1_dco;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco;
TIMESPEC TS_adc1_dco = PERIOD "adc1_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "gen_ddr_ctrl*/*/c?_pll_lock" TIG;
NET "gen_ddr_ctrl*/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "gen_ddr_ctrl*/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
NET "gen_ddr_ctrl*/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "ddr_rst[*]" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
NET "gen_ddr_ctrl[?].*/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "gen_ddr_ctrl[?].*/*/memc4_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
# No sync words used in FMC-ADC
#TIMESPEC TS_adc0_sync_word = FROM sync_word TO fs0_clk 30ns DATAPATHONLY;
#TIMESPEC TS_adc1_sync_word = FROM sync_word TO fs1_clk 30ns DATAPATHONLY;
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
View file @ 13aaea4b
......@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Keep Hierarchy" "Yes"
xilinx::project save
xilinx::project close
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v 0 → 100644
View file @ 13aaea4b
`define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h4000
`define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h6000
`define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
hdl/top/svec_ref_design/Manifest.py
View file @ 13aaea4b
files = [
"svec_ref_fmc_adc_100Ms.vhd",
"svec_carrier_csr.vhd",
"../../cheby/svec_ref_fmc_adc_100Ms_mmap.vhd",
]
fetchto = "../../ip_cores"
modules = {
"local" : [
"../../../",
],
"git" : [
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/svec.git",
],
}
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 13aaea4b
......@@ -35,23 +35,16 @@ use UNISIM.vcomponents.all;
library work;
use work.vme64x_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.synthesis_descriptor.all;
use work.svec_carrier_csr_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
entity svec_ref_fmc_adc_100Ms is
generic(
g_SIMULATION : integer := 0;
g_NB_FMC_SLOTS : natural := 2;
g_MULTISHOT_RAM_SIZE : natural := 8192;
g_CALIB_SOFT_IP : string := "TRUE";
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram");
port
(
......@@ -88,7 +81,7 @@ entity svec_ref_fmc_adc_100Ms is
pcbrev_i : in std_logic_vector(4 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_onewire_b : inout std_logic;
onewire_b : inout std_logic;
-- SFP
sfp_txp_o : out std_logic;
......@@ -114,10 +107,10 @@ entity svec_ref_fmc_adc_100Ms is
uart_txd_o : out std_logic;
-- GPIO
fp_gpio1_o : out std_logic; -- PPS output
fp_gpio2_o : out std_logic; -- not used
fp_gpio3_o : out std_logic; -- not used
fp_gpio4_o : out std_logic; -- not used
fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_b : out std_logic; -- not used
fp_gpio3_b : in std_logic; -- ext 10MHz clock input
fp_gpio4_b : in std_logic; -- ext PPS input
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
......@@ -127,7 +120,7 @@ entity svec_ref_fmc_adc_100Ms is
-- VME interface
------------------------------------------
vme_write_n_i : in std_logic;
vme_rst_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
......@@ -153,24 +146,43 @@ entity svec_ref_fmc_adc_100Ms is
------------------------------------------
-- DDR (banks 4 and 5)
------------------------------------------
ddr_a_o : out std_logic_vector(14*g_NB_FMC_SLOTS-1 downto 0);
ddr_ba_o : out std_logic_vector(3*g_NB_FMC_SLOTS-1 downto 0);
ddr_cas_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ck_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ck_p_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_cke_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_dq_b : inout std_logic_vector(16*g_NB_FMC_SLOTS-1 downto 0);
ddr_ldm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ldqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ldqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_odt_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ras_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_reset_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_rzq_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_we_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr4_a_o : out std_logic_vector(13 downto 0);
ddr4_ba_o : out std_logic_vector(2 downto 0);
ddr4_cas_n_o : out std_logic;
ddr4_ck_n_o : out std_logic;
ddr4_ck_p_o : out std_logic;
ddr4_cke_o : out std_logic;
ddr4_dq_b : inout std_logic_vector(15 downto 0);
ddr4_ldm_o : out std_logic;
ddr4_ldqs_n_b : inout std_logic;
ddr4_ldqs_p_b : inout std_logic;
ddr4_odt_o : out std_logic;
ddr4_ras_n_o : out std_logic;
ddr4_reset_n_o : out std_logic;
ddr4_rzq_b : inout std_logic;
ddr4_udm_o : out std_logic;
ddr4_udqs_n_b : inout std_logic;
ddr4_udqs_p_b : inout std_logic;
ddr4_we_n_o : out std_logic;
ddr5_a_o : out std_logic_vector(13 downto 0);
ddr5_ba_o : out std_logic_vector(2 downto 0);
ddr5_cas_n_o : out std_logic;
ddr5_ck_n_o : out std_logic;
ddr5_ck_p_o : out std_logic;
ddr5_cke_o : out std_logic;
ddr5_dq_b : inout std_logic_vector(15 downto 0);
ddr5_ldm_o : out std_logic;
ddr5_ldqs_n_b : inout std_logic;
ddr5_ldqs_p_b : inout std_logic;
ddr5_odt_o : out std_logic;
ddr5_ras_n_o : out std_logic;
ddr5_reset_n_o : out std_logic;
ddr5_rzq_b : inout std_logic;
ddr5_udm_o : out std_logic;
ddr5_udqs_n_b : inout std_logic;
ddr5_udqs_p_b : inout std_logic;
ddr5_we_n_o : out std_logic;
------------------------------------------
-- FMC slots
......@@ -213,156 +225,33 @@ entity svec_ref_fmc_adc_100Ms is
------------------------------------------
-- FMC slot management
------------------------------------------
fmc_prsnt_m2c_n_i : in std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); -- Mezzanine present (active low)
fmc_scl_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); -- Mezzanine system I2C clock (EEPROM)
fmc_sda_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0)); -- Mezzanine system I2C data (EEPROM)
end svec_ref_fmc_adc_100Ms;
fmc0_prsnt_m2c_n_i : in std_logic;
fmc1_prsnt_m2c_n_i : in std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic);
end svec_ref_fmc_adc_100Ms;
architecture rtl of svec_ref_fmc_adc_100Ms is
function f_ddr_bank_sel (
constant idx : natural)
return string is
begin
if idx = 0 then
return "SVEC_BANK4_64B_32B";
else
return "SVEC_BANK5_64B_32B";
end if;
end function f_ddr_bank_sel;
architecture arch of svec_ref_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
-- Constants declaration
------------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 9;
-- Wishbone master(s)
constant c_WB_MASTER_VME : integer := 0;
constant c_NUM_WB_SLAVES : integer := 3;
-- Wishbone slave(s)
-- IMPORTANT: FMC1 peripherals need always be at +3 index offset from the
-- respective FMC0 ones, in order for the FMC+DDR generating loop to work
constant c_WB_SLAVE_SVEC_CSR : integer := 0; -- SVEC control and status registers
constant c_WB_SLAVE_VIC : integer := 1; -- Vectored interrupt controller
constant c_WB_SLAVE_FMC0_ADC : integer := 2; -- FMC slot 1 ADC mezzanine
constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 3; -- FMC slot 1 DDR address
constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 4; -- FMC slot 1 DDR data
constant c_WB_SLAVE_FMC1_ADC : integer := 5; -- FMC slot 2 ADC mezzanine
constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 6; -- FMC slot 2 DDR address
constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 7; -- FMC slot 2 DDR data
constant c_WB_SLAVE_WR_CORE : integer := 8; -- WR PTP core
-- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
-- Devices sdb description
constant c_WB_SVEC_CSR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00006603",
version => x"00000001",
date => x"20121116",
name => "WB-SVEC-CSR ")));
constant c_WB_DDR_DAT_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"10006610",
version => x"00000001",
date => x"20130704",
name => "WB-DDR-Data-Access ")));
constant c_WB_DDR_ADR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000003",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"10006611",
version => x"00000001",
date => x"20130704",
name => "WB-DDR-Addr-Access ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_FMC0_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_FMC1_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_WR_CORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) :=
(
c_WB_SLAVE_SVEC_CSR => f_sdb_embed_device(c_WB_SVEC_CSR_SDB, x"00001200"),
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00001300"),
c_WB_SLAVE_FMC0_ADC => f_sdb_embed_bridge(c_FMC0_BRIDGE_SDB, x"00002000"),
c_WB_SLAVE_FMC0_DDR_ADR => f_sdb_embed_device(c_WB_DDR_ADR_SDB, x"00004000"),
c_WB_SLAVE_FMC0_DDR_DAT => f_sdb_embed_device(c_WB_DDR_DAT_SDB, x"00005000"),
c_WB_SLAVE_FMC1_ADC => f_sdb_embed_bridge(c_FMC1_BRIDGE_SDB, x"00006000"),
c_WB_SLAVE_FMC1_DDR_ADR => f_sdb_embed_device(c_WB_DDR_ADR_SDB, x"00008000"),
c_WB_SLAVE_FMC1_DDR_DAT => f_sdb_embed_device(c_WB_DDR_DAT_SDB, x"00009000"),
c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_WR_CORE_BRIDGE_SDB, x"00040000"),
c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO));
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00003500",
1 => x"00007500");
------------------------------------------------------------------------------
-- Other constants declaration
------------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- SVEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0002";
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC0_ADC : integer := 1; -- FMC slot 1 ADC mezzanine
constant c_WB_SLAVE_FMC1_ADC : integer := 2; -- FMC slot 2 ADC mezzanine
-- Conversion of g_simulation to string needed for DDR controller
function f_int2string (n : natural) return string is
begin
if n = 0 then
return "FALSE";
else
return "TRUE ";
end if;
end;
constant c_SIMULATION_STR : string := f_int2string(g_SIMULATION);
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
------------------------------------------------------------------------------
-- Signals declaration
......@@ -371,43 +260,17 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
subtype t_fmc_slot_vec is std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
-- Clocks and resets
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal areset_n : std_logic := '0';
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
signal rst_ddr_333m_n : std_logic := '0';
signal sw_rst_fmc : t_fmc_slot_vec := (others => '1');
signal sw_rst_fmc_sync : t_fmc_slot_vec := (others => '1');
signal fmc_rst_ref_n : t_fmc_slot_vec := (others => '0');
signal fmc_rst_sys_n : t_fmc_slot_vec := (others => '0');
signal ddr_rst : t_fmc_slot_vec := (others => '1');
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of clk_ddr_333m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal Vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal vme_access : std_logic;
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ext_ref : std_logic;
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
signal areset_n : std_logic := '0';
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
......@@ -421,313 +284,216 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
signal fmc_wb_ddr_in : t_wishbone_master_data64_in_array(g_NB_FMC_SLOTS-1 downto 0);
signal fmc_wb_ddr_out : t_wishbone_master_data64_out_array(g_NB_FMC_SLOTS-1 downto 0);
-- Interrupts and status
signal ddr_wr_fifo_empty : t_fmc_slot_vec;
signal irq_to_vme : std_logic;
signal fmc_irq : t_fmc_slot_vec;
signal fmc_acq_cfg_ok : t_fmc_slot_vec;
type t_fmc_acq_led is array (0 to g_NB_FMC_SLOTS-1) of std_logic_vector(1 downto 0);
-- Resync interrupts to sys domain
-- Interrupts and status
signal ddr_wr_fifo_empty : t_fmc_slot_vec;
signal ddr_wr_fifo_empty_sync : t_fmc_slot_vec;
signal fmc_irq_sync : t_fmc_slot_vec;
signal fmc_irq : t_fmc_slot_vec;
signal fmc_acq_trig : t_fmc_slot_vec;
signal fmc_acq_trig_sync : t_fmc_slot_vec;
signal fmc_acq_cfg_ok : t_fmc_slot_vec;
signal fmc_acq_cfg_ok_sync : t_fmc_slot_vec;
signal fmc_acq_led : t_fmc_acq_led;
signal irq_vector : t_fmc_slot_vec;
signal vme_access : std_logic;
-- Front panel LED control
signal svec_led : std_logic_vector(15 downto 0);
signal led_state : std_logic_vector(15 downto 0);
signal led_state_csr : std_logic_vector(15 downto 0);
-- DDR
type t_fmc_adc_ddr_status_array is array (natural range <>) of std_logic_vector(31 downto 0);
type t_fmc_adc_ddr_addr_cnt_array is array (natural range <>) of unsigned(31 downto 0);
signal ddr_status : t_fmc_adc_ddr_status_array(g_NB_FMC_SLOTS-1 downto 0);
signal ddr_calib_done : t_fmc_slot_vec;
signal ddr_addr_cnt : t_fmc_adc_ddr_addr_cnt_array(g_NB_FMC_SLOTS-1 downto 0);
signal ddr_dat_cyc_d : t_fmc_slot_vec;
signal ddr_addr_cnt_en : t_fmc_slot_vec;
-- SFP
signal sfp_scl_out : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_sda_in : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- White Rabbit
signal wrabbit_en : std_logic;
signal wrc_scl_out : std_logic;
signal wrc_scl_in : std_logic;
signal wrc_sda_out : std_logic;
signal wrc_sda_in : std_logic;
signal pps : std_logic;
signal pps_led : std_logic;
signal wr_led_act : std_logic;
signal wr_led_link : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
-- WR PTP core timing interface
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
-- IO for CSR registers
signal csr_regin : t_carrier_csr_master_in;
signal csr_regout : t_carrier_csr_master_out;
begin
------------------------------------------------------------------------------
-- Reset logic
------------------------------------------------------------------------------
areset_n <= vme_rst_n_i and rst_n_i;
sys_clk_pll_locked <= '1';
gen_fmc_rst : for I in 0 to g_NB_FMC_SLOTS-1 generate
-- reset for mezzanines
-- including soft reset, with re-sync from 62.5MHz domain
cmp_fmc_sw_reset_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => sw_rst_fmc(I),
synced_o => sw_rst_fmc_sync(I));
fmc_rst_ref_n(I) <= rst_ref_125m_n and not sw_rst_fmc_sync(I);
fmc_rst_sys_n(I) <= rst_sys_62m5_n and not sw_rst_fmc(I);
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst(I) <= not rst_ddr_333m_n or sw_rst_fmc(I);
end generate gen_fmc_rst;
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
cmp_vme_core : xvme64x_core
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_time_valid_sync : std_logic;
signal wrabbit_en : std_logic;
signal pps : std_logic;
signal pps_led : std_logic;
signal pps_ext_in : std_logic;
signal wr_led_link : std_logic;
signal wr_led_act : std_logic;
begin -- architecture arch
areset_n <= vme_sysreset_n_i and rst_n_i;
inst_svec_base : entity work.svec_base_wr
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR4 => TRUE,
g_WITH_DDR5 => TRUE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 2,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 0,
g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_rst_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_master_out(c_WB_MASTER_VME),
wb_i => cnx_master_in(c_WB_MASTER_VME),
int_i => irq_to_vme);
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
rst_n_i => areset_n,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
pps_ext_i => pps_ext_in,
vme_write_n_i => vme_write_n_i,
vme_sysreset_n_i => vme_sysreset_n_i,
vme_retry_oe_o => vme_retry_oe_o,
vme_retry_n_o => vme_retry_n_o,
vme_lword_n_b => vme_lword_n_b,
vme_iackout_n_o => vme_iackout_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_gap_i => vme_gap_i,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_ds_n_i => vme_ds_n_i,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
vme_as_n_i => vme_as_n_i,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
vme_irq_o => vme_irq_o,
vme_ga_i => vme_ga_i,
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc1_scl_b => fmc1_scl_b,
fmc1_sda_b => fmc1_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i,
onewire_b => onewire_b,
carrier_scl_b => carrier_scl_b,
carrier_sda_b => carrier_sda_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => pll20dac_sclk_o,
plldac_din_o => pll20dac_din_o,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr4_a_o => ddr4_a_o,
ddr4_ba_o => ddr4_ba_o,
ddr4_cas_n_o => ddr4_cas_n_o,
ddr4_ck_n_o => ddr4_ck_n_o,
ddr4_ck_p_o => ddr4_ck_p_o,
ddr4_cke_o => ddr4_cke_o,
ddr4_dq_b => ddr4_dq_b,
ddr4_ldm_o => ddr4_ldm_o,
ddr4_ldqs_n_b => ddr4_ldqs_n_b,
ddr4_ldqs_p_b => ddr4_ldqs_p_b,
ddr4_odt_o => ddr4_odt_o,
ddr4_ras_n_o => ddr4_ras_n_o,
ddr4_reset_n_o => ddr4_reset_n_o,
ddr4_rzq_b => ddr4_rzq_b,
ddr4_udm_o => ddr4_udm_o,
ddr4_udqs_n_b => ddr4_udqs_n_b,
ddr4_udqs_p_b => ddr4_udqs_p_b,
ddr4_we_n_o => ddr4_we_n_o,
ddr5_a_o => ddr5_a_o,
ddr5_ba_o => ddr5_ba_o,
ddr5_cas_n_o => ddr5_cas_n_o,
ddr5_ck_n_o => ddr5_ck_n_o,
ddr5_ck_p_o => ddr5_ck_p_o,
ddr5_cke_o => ddr5_cke_o,
ddr5_dq_b => ddr5_dq_b,
ddr5_ldm_o => ddr5_ldm_o,
ddr5_ldqs_n_b => ddr5_ldqs_n_b,
ddr5_ldqs_p_b => ddr5_ldqs_p_b,
ddr5_odt_o => ddr5_odt_o,
ddr5_ras_n_o => ddr5_ras_n_o,
ddr5_reset_n_o => ddr5_reset_n_o,
ddr5_rzq_b => ddr5_rzq_b,
ddr5_udm_o => ddr5_udm_o,
ddr5_udqs_n_b => ddr5_udqs_n_b,
ddr5_udqs_p_b => ddr5_udqs_p_b,
ddr5_we_n_o => ddr5_we_n_o,
pcbrev_i => pcbrev_i,
ddr4_clk_i => clk_ref_125m,
ddr4_rst_n_i => rst_ref_125m_n,
ddr4_wb_i => fmc_wb_ddr_out(0),
ddr4_wb_o => fmc_wb_ddr_in(0),
ddr5_clk_i => clk_ref_125m,
ddr5_rst_n_i => rst_ref_125m_n,
ddr5_wb_i => fmc_wb_ddr_out(1),
ddr5_wb_o => fmc_wb_ddr_in(1),
ddr4_wr_fifo_empty_o => ddr_wr_fifo_empty(0),
ddr5_wr_fifo_empty_o => ddr_wr_fifo_empty(1),
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => pps,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
app_wb_o => cnx_master_out,
app_wb_i => cnx_master_in);
------------------------------------------------------------------------------
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_WRAPAROUND => TRUE,
g_LAYOUT => c_INTERCONNECT_LAYOUT,
g_SDB_ADDR => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
-------------------------------------------------------------------------------
-- White Rabbit Core (SVEC board package)
-------------------------------------------------------------------------------
-- Tristates for Carrier EEPROM
carrier_scl_b <= '0' when (wrc_scl_out = '0') else 'Z';
carrier_sda_b <= '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= carrier_scl_b;
wrc_sda_in <= carrier_sda_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for Carrier OneWire
carrier_onewire_b <= '0' when onewire_oe = '1' else 'Z';
onewire_data <= carrier_onewire_b;
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_SIMULATION => g_SIMULATION,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_FABRIC_IFACE => PLAIN)
cmp_crossbar : entity work.spec_ref_fmc_adc_100m_mmap
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => wrc_sda_in,
eeprom_sda_o => wrc_sda_out,
eeprom_scl_i => wrc_scl_in,
eeprom_scl_o => wrc_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WR_CORE),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WR_CORE),
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => pps,
pps_led_o => pps_led,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
link_ok_o => wrabbit_en);
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => cnx_master_out,
wb_o => cnx_master_in,
metadata_i => cnx_slave_out(c_WB_SLAVE_METADATA),
metadata_o => cnx_slave_in(c_WB_SLAVE_METADATA),
fmc1_adc_mezzanine_i => cnx_slave_out(c_WB_SLAVE_FMC0_ADC),
fmc1_adc_mezzanine_o => cnx_slave_in(c_WB_SLAVE_FMC0_ADC),
fmc2_adc_mezzanine_i => cnx_slave_out(c_WB_SLAVE_FMC1_ADC),
fmc2_adc_mezzanine_o => cnx_slave_in(c_WB_SLAVE_FMC1_ADC));
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Carrier status (PLL, FMC presence)
-- Front panel LED manual control
-- Application-specific metadata ROM
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.svec_carrier_csr
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR),
wb_o => cnx_slave_out(c_WB_SLAVE_SVEC_CSR),
carrier_csr_i => csr_regin,
carrier_csr_o => csr_regout);
csr_regin.carrier_pcb_rev <= pcbrev_i;
csr_regin.carrier_reserved <= (others => '0');
csr_regin.carrier_type <= c_CARRIER_TYPE;
csr_regin.stat_fmc0_pres <= fmc_prsnt_m2c_n_i(0);
csr_regin.stat_fmc1_pres <= fmc_prsnt_m2c_n_i(1);
csr_regin.stat_sys_pll_lck <= sys_clk_pll_locked;
csr_regin.stat_ddr0_cal_done <= ddr_calib_done(0);
csr_regin.stat_ddr1_cal_done <= ddr_calib_done(1);
led_state_csr <= csr_regout.ctrl_fp_leds_man;
sw_rst_fmc(0) <= csr_regout.rst_fmc0;
sw_rst_fmc(1) <= csr_regout.rst_fmc1;
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
------------------------------------------------------------------------------
gen_fmc_irq : for I in 0 to g_NB_FMC_SLOTS - 1 generate
cmp_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq(I),
synced_o => fmc_irq_sync(I));
end generate gen_fmc_irq;
cmp_vic : xwb_vic
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_INTERFACE_MODE => PIPELINED,
g_ADDRESS_GRANULARITY => BYTE,
g_NUM_INTERRUPTS => 2,
g_INIT_VECTORS => c_VIC_VECTOR_TABLE)
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4302", -- "ADC2"
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_irq_sync(0),
irqs_i(1) => fmc_irq_sync(1),
irq_master_o => irq_to_vme);
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking)
......@@ -738,16 +504,26 @@ begin
-- Mezzanine 1-wire master
------------------------------------------------------------------------------
cmp_tm_time_valid_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
gen_fmc_mezzanine : for I in 0 to g_NB_FMC_SLOTS - 1 generate
cmp_xwb_clock_bridge : xwb_clock_bridge
generic map (
g_SLAVE_PORT_WB_MODE => CLASSIC,
g_MASTER_PORT_WB_MODE => PIPELINED)
port map (
slave_clk_i => clk_sys_62m5,
slave_rst_n_i => fmc_rst_sys_n(I),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC0_ADC + 3*I),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC0_ADC + 3*I),
slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_FMC0_ADC + I),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC0_ADC + I),
master_clk_i => clk_ref_125m,
master_rst_n_i => fmc_rst_ref_n(I),
master_rst_n_i => rst_ref_125m_n,
master_i => cnx_fmc_sync_master_in(I),
master_o => cnx_fmc_sync_master_out(I));
......@@ -758,25 +534,33 @@ begin
data_i => ddr_wr_fifo_empty(I),
synced_o => ddr_wr_fifo_empty_sync(I));
cmp_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq(I),
synced_o => irq_vector(I));
cmp_fmc_adc_mezzanine : fmc_adc_mezzanine
generic map (
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
g_SPARTAN6_USE_PLL => TRUE,
g_WB_MODE => PIPELINED,
g_WB_GRANULARITY => BYTE)
port map (
sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc_rst_ref_n(I),
sys_rst_n_i => rst_ref_125m_n,
wb_csr_slave_i => cnx_fmc_sync_master_out(I),
wb_csr_slave_o => cnx_fmc_sync_master_in(I),
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_rst_n_i => fmc_rst_ref_n(I),
wb_ddr_rst_n_i => rst_ref_125m_n,
wb_ddr_master_i => fmc_wb_ddr_in(I),
wb_ddr_master_o => fmc_wb_ddr_out(I),
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty_sync(I),
trig_irq_o => open,
trig_irq_o => fmc_acq_trig(I),
acq_end_irq_o => open,
eic_irq_o => fmc_irq(I),
acq_cfg_ok_o => fmc_acq_cfg_ok(I),
......@@ -816,179 +600,14 @@ begin
mezz_one_wire_b => adc_one_wire_b(I),
sys_scl_b => fmc_scl_b(I),
sys_sda_b => fmc_sda_b(I),
wr_tm_link_up_i => tm_link_up,
wr_tm_time_valid_i => tm_time_valid,
wr_tm_time_valid_i => tm_time_valid_sync,
wr_tm_tai_i => tm_tai,
wr_tm_cycles_i => tm_cycles,
wr_enable_i => wrabbit_en);
end generate gen_fmc_mezzanine;
------------------------------------------------------------------------------
-- DDR controllers (banks 4 and 5)
------------------------------------------------------------------------------
gen_ddr_ctrl : for I in 0 to g_NB_FMC_SLOTS - 1 generate
cmp_ddr_ctrl_bank : ddr3_ctrl
generic map (
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => f_ddr_bank_sel(I),
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_SIMULATION_STR,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => ddr_rst(I),
status_o => ddr_status(I),
ddr3_dq_b => ddr_dq_b(16*(I+1)-1 downto 16*I),
ddr3_a_o => ddr_a_o(14*(I+1)-1 downto 14*I),
ddr3_ba_o => ddr_ba_o(3*(I+1)-1 downto 3*I),
ddr3_ras_n_o => ddr_ras_n_o(I),
ddr3_cas_n_o => ddr_cas_n_o(I),
ddr3_we_n_o => ddr_we_n_o(I),
ddr3_odt_o => ddr_odt_o(I),
ddr3_rst_n_o => ddr_reset_n_o(I),
ddr3_cke_o => ddr_cke_o(I),
ddr3_dm_o => ddr_ldm_o(I),
ddr3_udm_o => ddr_udm_o(I),
ddr3_dqs_p_b => ddr_ldqs_p_b(I),
ddr3_dqs_n_b => ddr_ldqs_n_b(I),
ddr3_udqs_p_b => ddr_udqs_p_b(I),
ddr3_udqs_n_b => ddr_udqs_n_b(I),
ddr3_clk_p_o => ddr_ck_p_o(I),
ddr3_clk_n_o => ddr_ck_n_o(I),
ddr3_rzq_b => ddr_rzq_b(I),
wb0_rst_n_i => fmc_rst_ref_n(I),
wb0_clk_i => clk_ref_125m,
wb0_sel_i => fmc_wb_ddr_out(I).sel,
wb0_cyc_i => fmc_wb_ddr_out(I).cyc,
wb0_stb_i => fmc_wb_ddr_out(I).stb,
wb0_we_i => fmc_wb_ddr_out(I).we,
wb0_addr_i => fmc_wb_ddr_out(I).adr,
wb0_data_i => fmc_wb_ddr_out(I).dat,
wb0_data_o => fmc_wb_ddr_in(I).dat,
wb0_ack_o => fmc_wb_ddr_in(I).ack,
wb0_stall_o => fmc_wb_ddr_in(I).stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty(I),
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).sel,
wb1_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).cyc,
wb1_stb_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).stb,
wb1_we_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).we,
wb1_data_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).dat,
wb1_addr_i => std_logic_vector(ddr_addr_cnt(I)),
wb1_data_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).dat,
wb1_ack_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).ack,
wb1_stall_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
fmc_wb_ddr_in(I).err <= '0';
fmc_wb_ddr_in(I).rty <= '0';
ddr_calib_done(I) <= ddr_status(I)(0);
-- DDR address counter
-- The address counter is set by writing to the c_WB_SLAVE_FMC_DDR_ADR wb peripheral.
-- Then the counter is incremented on every access to the c_WB_SLAVE_FMC_DDR_DAT wb peripheral.
-- The counter is incremented on the falling edge of cyc. This is because the ddr controller
-- samples the address on (cyc_re and stb)+1
p_ddr_dat_cyc : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr_dat_cyc_d(I) <= '0';
else
ddr_dat_cyc_d(I) <= cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).cyc;
end if;
end if;
end process p_ddr_dat_cyc;
ddr_addr_cnt_en(I) <= not(cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).cyc) and ddr_dat_cyc_d(I);
-- address counter
p_ddr_addr_cnt : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr_addr_cnt(I) <= (others => '0');
elsif (cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).we = '1' and
cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).stb = '1' and
cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).cyc = '1') then
ddr_addr_cnt(I) <= unsigned(cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).dat);
elsif (ddr_addr_cnt_en(I) = '1') then
ddr_addr_cnt(I) <= ddr_addr_cnt(I) + 1;
end if;
end if;
end process p_ddr_addr_cnt;
-- ack generation
p_ddr_addr_ack : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).ack <= '0';
elsif (cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).stb = '1' and
cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).cyc = '1') then
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).ack <= '1';
else
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).ack <= '0';
end if;
end if;
end process p_ddr_addr_ack;
-- Address counter read back
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).dat <= std_logic_vector(ddr_addr_cnt(I));
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).err <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).err <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).stall <= '0';
end generate gen_ddr_ctrl;
------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------
......@@ -1013,7 +632,7 @@ begin
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc,
pulse_i => cnx_master_out.cyc,
extended_o => vme_access);
gen_fmc_led : for I in 0 to g_NB_FMC_SLOTS - 1 generate
......@@ -1025,33 +644,48 @@ begin
data_i => fmc_acq_cfg_ok(I),
synced_o => fmc_acq_cfg_ok_sync(I));
end generate gen_fmc_led;
cmp_fmc_trig_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_acq_trig(I),
synced_o => fmc_acq_trig_sync(I));
-- Logic OR of signals and CSR register for LED control
svec_led <= led_state or led_state_csr;
p_fmc_acq_led: process (fmc_acq_cfg_ok_sync) is
begin
if fmc_acq_cfg_ok_sync(I) = '0' then
fmc_acq_led(I) <= c_LED_RED;
elsif fmc_acq_trig_sync(I) = '1' then
fmc_acq_led(I) <= c_LED_RED_GREEN;
else
fmc_acq_led(I) <= c_LED_GREEN;
end if;
end process p_fmc_acq_led;
end generate gen_fmc_led;
-- LED order on front panel (top to bottom)
-- 1..0 | 9..8
-- 3..2 | 11..10
-- 5..4 | 13..12
-- 7..6 | 15..14
led_state(1 downto 0) <= c_led_off;
led_state(3 downto 2) <= c_led_green when fmc_acq_cfg_ok_sync(0) = '1' else c_led_red;
led_state(5 downto 4) <= c_led_green when pps_led = '1' else c_led_off;
led_state(7 downto 6) <= c_led_green when wr_led_link = '1' else c_led_red;
led_state(9 downto 8) <= c_led_red_green when vme_access = '1' else c_led_off;
led_state(11 downto 10) <= c_led_green when fmc_acq_cfg_ok_sync(1) = '1' else c_led_red;
led_state(13 downto 12) <= c_led_green when tm_time_valid = '1' else c_led_red;
led_state(15 downto 14) <= c_led_red_green when wr_led_act = '1' else c_led_off;
svec_led(1 downto 0) <= c_LED_GREEN when wr_led_link = '1' else c_LED_RED;
svec_led(3 downto 2) <= fmc_acq_led(1);
svec_led(5 downto 4) <= c_LED_GREEN when tm_time_valid = '1'else c_LED_RED;
svec_led(7 downto 6) <= c_LED_RED_GREEN when vme_access = '1' else c_LED_OFF;
svec_led(9 downto 8) <= c_LED_RED_GREEN when wr_led_act = '1' else c_LED_OFF;
svec_led(11 downto 10) <= fmc_acq_led(0);
svec_led(13 downto 12) <= c_LED_OFF;
svec_led(15 downto 14) <= c_LED_GREEN when pps_led = '1' else c_LED_OFF;
-- Front panel IO configuration
fp_gpio1_o <= pps;
fp_gpio2_o <= '0';
fp_gpio3_o <= '0';
fp_gpio4_o <= '0';
fp_gpio1_b <= pps;
fp_gpio2_b <= '0';
clk_ext_ref <= fp_gpio3_b;
pps_ext_in <= fp_gpio4_b;
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '1';
fp_gpio34_a2b_o <= '0';
end rtl;
end architecture arch;
software/drivers/Kbuild
View file @ 13aaea4b
......@@ -12,7 +12,7 @@ ccflags-y += -DDRV_VERSION=\"$(DRV_VERSION)\"
ccflags-y += -Wall -Werror
obj-m := fmc-adc-100m-ref-spec.o
#obj-m += fmc-adc-100m-ref-svec.o
obj-m += fmc-adc-100m-ref-svec.o
fmc-adc-100m-ref-spec-objs := fmc-adc-100m-ref-spec-core.o
#fmc-adc-100m-ref-svec-objs := fmc-adc-100m-ref-svec-core.o
fmc-adc-100m-ref-svec-objs := fmc-adc-100m-ref-svec-core.o
software/drivers/fmc-adc-100m-ref-svec-core.c 0 → 100644
View file @ 13aaea4b
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mod_devicetable.h>
enum ft_svec_dev_offsets {
FT_SVEC_FA100_S1_MEM_START = 0x00002000,
FT_SVEC_FA100_S1_MEM_END = 0x00003A00,
FT_SVEC_FA100_S2_MEM_START = 0x00004000,
FT_SVEC_FA100_S2_MEM_END = 0x00005A00,
};
/* MFD devices */
enum svec_fpga_mfd_devs_enum {
FT_SVEC_MFD_FA100_S1,
FT_SVEC_MFD_FA100_S2,
};
static struct resource ft_svec_fdt100_res_s1[] = {
{
.name = "fmc-adc-100m14b4ch-mem",
.flags = IORESOURCE_MEM,
.start = FT_SVEC_FA100_S1_MEM_START,
.end = FT_SVEC_FA100_S1_MEM_END,
}, {
.name = "fmc-adc-100m14b4ch-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
static struct resource ft_svec_fdt100_res_s2[] = {
{
.name = "fmc-adc-100m14b4ch-mem",
.flags = IORESOURCE_MEM,
.start = FT_SVEC_FA100_S2_MEM_START,
.end = FT_SVEC_FA100_S2_MEM_END,
}, {
.name = "fmc-adc-100m14b4ch-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 1,
.end = 1,
},
};
static const struct mfd_cell ft_svec_mfd_devs[] = {
[FT_SVEC_MFD_FA100_S1] = {
.name = "adc-100m-svec",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(ft_svec_fdt100_res_s1),
.resources = ft_svec_fdt100_res_s1,
},
[FT_SVEC_MFD_FA100_S2] = {
.name = "adc-100m-svec",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(ft_svec_fdt100_res_s2),
.resources = ft_svec_fdt100_res_s2,
},
};
static int ft_svec_probe(struct platform_device *pdev)
{
struct resource *rmem;
int irq;
rmem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!rmem) {
dev_err(&pdev->dev, "Missing memory resource\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "Missing IRQ number\n");
return -EINVAL;
}
/*
* We know that this design uses the HTVIC IRQ controller.
* This IRQ controller has a linear mapping, so it is enough
* to give the first one as input
*/
return mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
ft_svec_mfd_devs,
ARRAY_SIZE(ft_svec_mfd_devs),
rmem, irq, NULL);
}
static int ft_svec_remove(struct platform_device *pdev)
{
mfd_remove_devices(&pdev->dev);
return 0;
}
static const struct platform_device_id ft_svec_id_table[] = {
{
.name = "fmc-adc-100m-svec",
.driver_data = 0,
}, {
.name = "id:000010DC41444302",
.driver_data = 0,
}, {
.name = "id:000010dc41444302",
.driver_data = 0,
},
{},
};
static struct platform_driver ft_svec_driver = {
.driver = {
.name = "fmc-adc-100m-svec",
.owner = THIS_MODULE,
},
.id_table = ft_svec_id_table,
.probe = ft_svec_probe,
.remove = ft_svec_remove,
};
module_platform_driver(ft_svec_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Driver for the FMC ADC 100M SVEC REF");
MODULE_DEVICE_TABLE(platform, ft_svec_id_table);
MODULE_SOFTDEP("pre: svec_fmc_carrier fmc-adc-100m14b4ch");
software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
View file @ 13aaea4b
#ifndef __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
/* a ROM containing the application metadata */
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
/* FMC ADC Mezzanine slot 1 */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0x4000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
/* FMC ADC Mezzanine slot 2 */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0x6000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
struct spec_ref_fmc_adc_100m_mmap {
/* padding to: 2048 words */
uint32_t __padding_0[2048];
/* [0x2000]: SUBMAP a ROM containing the application metadata */
uint32_t metadata[16];
/* padding to: 4096 words */
uint32_t __padding_1[2032];
/* [0x4000]: SUBMAP FMC ADC Mezzanine slot 1 */
struct fmc_adc_mezzanine_mmap fmc1_adc_mezzanine;
/* [0x6000]: SUBMAP FMC ADC Mezzanine slot 2 */
struct fmc_adc_mezzanine_mmap fmc2_adc_mezzanine;
};
#endif /* __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__ */
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