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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
13aaea4b
Commit
13aaea4b
authored
Dec 16, 2019
by
Dimitris Lampridis
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[svec] migrate design to the Convention
parent
f54f430a
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15 changed files
with
816 additions
and
1227 deletions
+816
-1227
.gitmodules
.gitmodules
+3
-0
svec_ref_fmc_adc_100Ms_mmap.cheby
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
+26
-0
svec_ref_fmc_adc_100Ms_mmap.vhd
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
+233
-0
general-cores
hdl/ip_cores/general-cores
+1
-1
svec
hdl/ip_cores/svec
+1
-0
vme64x-core
hdl/ip_cores/vme64x-core
+1
-1
Manifest.py
hdl/syn/svec_ref_design_wr/Manifest.py
+15
-14
svec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
+24
-525
syn_extra_steps.tcl
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
+2
-0
svec_ref_fmc_adc_100Ms_mmap.v
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
+7
-0
Manifest.py
hdl/top/svec_ref_design/Manifest.py
+10
-1
svec_ref_fmc_adc_100Ms.vhd
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+317
-683
Kbuild
software/drivers/Kbuild
+2
-2
fmc-adc-100m-ref-svec-core.c
software/drivers/fmc-adc-100m-ref-svec-core.c
+138
-0
svec_ref_fmc_adc_100Ms_mmap.h
software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h
+36
-0
No files found.
.gitmodules
View file @
13aaea4b
...
...
@@ -16,3 +16,6 @@
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
0 → 100644
View file @
13aaea4b
memory-map:
name: spec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x8000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
address: 0x2000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: fmc1_adc_mezzanine
address: 0x4000
description: FMC ADC Mezzanine slot 1
filename: fmc_adc_mezzanine_mmap.cheby
- submap:
name: fmc2_adc_mezzanine
address: 0x6000
description: FMC ADC Mezzanine slot 2
filename: fmc_adc_mezzanine_mmap.cheby
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
0 → 100644
View file @
13aaea4b
-- Do not edit; this file was generated by Cheby using these options:
-- -i svec_ref_fmc_adc_100Ms_mmap.cheby --gen-hdl=svec_ref_fmc_adc_100Ms_mmap.vhd
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
spec_ref_fmc_adc_100m_mmap
is
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
;
-- a ROM containing the application metadata
metadata_i
:
in
t_wishbone_master_in
;
metadata_o
:
out
t_wishbone_master_out
;
-- FMC ADC Mezzanine slot 1
fmc1_adc_mezzanine_i
:
in
t_wishbone_master_in
;
fmc1_adc_mezzanine_o
:
out
t_wishbone_master_out
;
-- FMC ADC Mezzanine slot 2
fmc2_adc_mezzanine_i
:
in
t_wishbone_master_in
;
fmc2_adc_mezzanine_o
:
out
t_wishbone_master_out
);
end
spec_ref_fmc_adc_100m_mmap
;
architecture
syn
of
spec_ref_fmc_adc_100m_mmap
is
signal
rd_int
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_ack_int
:
std_logic
;
signal
wr_ack_int
:
std_logic
;
signal
wb_en
:
std_logic
;
signal
ack_int
:
std_logic
;
signal
wb_rip
:
std_logic
;
signal
wb_wip
:
std_logic
;
signal
metadata_re
:
std_logic
;
signal
metadata_wt
:
std_logic
;
signal
metadata_rt
:
std_logic
;
signal
metadata_tr
:
std_logic
;
signal
metadata_wack
:
std_logic
;
signal
metadata_rack
:
std_logic
;
signal
fmc1_adc_mezzanine_re
:
std_logic
;
signal
fmc1_adc_mezzanine_wt
:
std_logic
;
signal
fmc1_adc_mezzanine_rt
:
std_logic
;
signal
fmc1_adc_mezzanine_tr
:
std_logic
;
signal
fmc1_adc_mezzanine_wack
:
std_logic
;
signal
fmc1_adc_mezzanine_rack
:
std_logic
;
signal
fmc2_adc_mezzanine_re
:
std_logic
;
signal
fmc2_adc_mezzanine_wt
:
std_logic
;
signal
fmc2_adc_mezzanine_rt
:
std_logic
;
signal
fmc2_adc_mezzanine_tr
:
std_logic
;
signal
fmc2_adc_mezzanine_wack
:
std_logic
;
signal
fmc2_adc_mezzanine_rack
:
std_logic
;
signal
reg_rdat_int
:
std_logic_vector
(
31
downto
0
);
signal
rd_ack1_int
:
std_logic
;
begin
-- WB decode signals
wb_en
<=
wb_i
.
cyc
and
wb_i
.
stb
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_rip
<=
'0'
;
else
wb_rip
<=
(
wb_rip
or
(
wb_en
and
not
wb_i
.
we
))
and
not
rd_ack_int
;
end
if
;
end
if
;
end
process
;
rd_int
<=
(
wb_en
and
not
wb_i
.
we
)
and
not
wb_rip
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_wip
<=
'0'
;
else
wb_wip
<=
(
wb_wip
or
(
wb_en
and
wb_i
.
we
))
and
not
wr_ack_int
;
end
if
;
end
if
;
end
process
;
wr_int
<=
(
wb_en
and
wb_i
.
we
)
and
not
wb_wip
;
ack_int
<=
rd_ack_int
or
wr_ack_int
;
wb_o
.
ack
<=
ack_int
;
wb_o
.
stall
<=
not
ack_int
and
wb_en
;
wb_o
.
rty
<=
'0'
;
wb_o
.
err
<=
'0'
;
-- Assign outputs
-- Assignments for submap metadata
metadata_tr
<=
metadata_wt
or
metadata_rt
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
metadata_rt
<=
'0'
;
else
metadata_rt
<=
(
metadata_rt
or
metadata_re
)
and
not
metadata_rack
;
end
if
;
end
if
;
end
process
;
metadata_o
.
cyc
<=
metadata_tr
;
metadata_o
.
stb
<=
metadata_tr
;
metadata_wack
<=
metadata_i
.
ack
and
metadata_wt
;
metadata_rack
<=
metadata_i
.
ack
and
metadata_rt
;
metadata_o
.
adr
<=
((
25
downto
0
=>
'0'
)
&
wb_i
.
adr
(
5
downto
2
))
&
(
1
downto
0
=>
'0'
);
metadata_o
.
sel
<=
(
others
=>
'1'
);
metadata_o
.
we
<=
metadata_wt
;
metadata_o
.
dat
<=
wb_i
.
dat
;
-- Assignments for submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_tr
<=
fmc1_adc_mezzanine_wt
or
fmc1_adc_mezzanine_rt
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
fmc1_adc_mezzanine_rt
<=
'0'
;
else
fmc1_adc_mezzanine_rt
<=
(
fmc1_adc_mezzanine_rt
or
fmc1_adc_mezzanine_re
)
and
not
fmc1_adc_mezzanine_rack
;
end
if
;
end
if
;
end
process
;
fmc1_adc_mezzanine_o
.
cyc
<=
fmc1_adc_mezzanine_tr
;
fmc1_adc_mezzanine_o
.
stb
<=
fmc1_adc_mezzanine_tr
;
fmc1_adc_mezzanine_wack
<=
fmc1_adc_mezzanine_i
.
ack
and
fmc1_adc_mezzanine_wt
;
fmc1_adc_mezzanine_rack
<=
fmc1_adc_mezzanine_i
.
ack
and
fmc1_adc_mezzanine_rt
;
fmc1_adc_mezzanine_o
.
adr
<=
((
18
downto
0
=>
'0'
)
&
wb_i
.
adr
(
12
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc1_adc_mezzanine_o
.
sel
<=
(
others
=>
'1'
);
fmc1_adc_mezzanine_o
.
we
<=
fmc1_adc_mezzanine_wt
;
fmc1_adc_mezzanine_o
.
dat
<=
wb_i
.
dat
;
-- Assignments for submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_tr
<=
fmc2_adc_mezzanine_wt
or
fmc2_adc_mezzanine_rt
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
fmc2_adc_mezzanine_rt
<=
'0'
;
else
fmc2_adc_mezzanine_rt
<=
(
fmc2_adc_mezzanine_rt
or
fmc2_adc_mezzanine_re
)
and
not
fmc2_adc_mezzanine_rack
;
end
if
;
end
if
;
end
process
;
fmc2_adc_mezzanine_o
.
cyc
<=
fmc2_adc_mezzanine_tr
;
fmc2_adc_mezzanine_o
.
stb
<=
fmc2_adc_mezzanine_tr
;
fmc2_adc_mezzanine_wack
<=
fmc2_adc_mezzanine_i
.
ack
and
fmc2_adc_mezzanine_wt
;
fmc2_adc_mezzanine_rack
<=
fmc2_adc_mezzanine_i
.
ack
and
fmc2_adc_mezzanine_rt
;
fmc2_adc_mezzanine_o
.
adr
<=
((
18
downto
0
=>
'0'
)
&
wb_i
.
adr
(
12
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc2_adc_mezzanine_o
.
sel
<=
(
others
=>
'1'
);
fmc2_adc_mezzanine_o
.
we
<=
fmc2_adc_mezzanine_wt
;
fmc2_adc_mezzanine_o
.
dat
<=
wb_i
.
dat
;
-- Process for write requests.
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wr_ack_int
<=
'0'
;
metadata_wt
<=
'0'
;
fmc1_adc_mezzanine_wt
<=
'0'
;
fmc2_adc_mezzanine_wt
<=
'0'
;
else
wr_ack_int
<=
'0'
;
metadata_wt
<=
'0'
;
fmc1_adc_mezzanine_wt
<=
'0'
;
fmc2_adc_mezzanine_wt
<=
'0'
;
case
wb_i
.
adr
(
14
downto
13
)
is
when
"01"
=>
-- Submap metadata
metadata_wt
<=
(
metadata_wt
or
wr_int
)
and
not
metadata_wack
;
wr_ack_int
<=
metadata_wack
;
when
"10"
=>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_wt
<=
(
fmc1_adc_mezzanine_wt
or
wr_int
)
and
not
fmc1_adc_mezzanine_wack
;
wr_ack_int
<=
fmc1_adc_mezzanine_wack
;
when
"11"
=>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_wt
<=
(
fmc2_adc_mezzanine_wt
or
wr_int
)
and
not
fmc2_adc_mezzanine_wack
;
wr_ack_int
<=
fmc2_adc_mezzanine_wack
;
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
end
if
;
end
if
;
end
process
;
-- Process for registers read.
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
rd_ack1_int
<=
'0'
;
else
reg_rdat_int
<=
(
others
=>
'0'
);
case
wb_i
.
adr
(
14
downto
13
)
is
when
"01"
=>
when
"10"
=>
when
"11"
=>
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
end
if
;
end
if
;
end
process
;
-- Process for read requests.
process
(
wb_i
.
adr
,
reg_rdat_int
,
rd_ack1_int
,
rd_int
,
rd_int
,
metadata_i
.
dat
,
metadata_rack
,
metadata_rt
,
rd_int
,
fmc1_adc_mezzanine_i
.
dat
,
fmc1_adc_mezzanine_rack
,
fmc1_adc_mezzanine_rt
,
rd_int
,
fmc2_adc_mezzanine_i
.
dat
,
fmc2_adc_mezzanine_rack
,
fmc2_adc_mezzanine_rt
)
begin
-- By default ack read requests
wb_o
.
dat
<=
(
others
=>
'0'
);
metadata_re
<=
'0'
;
fmc1_adc_mezzanine_re
<=
'0'
;
fmc2_adc_mezzanine_re
<=
'0'
;
case
wb_i
.
adr
(
14
downto
13
)
is
when
"01"
=>
-- Submap metadata
metadata_re
<=
rd_int
;
wb_o
.
dat
<=
metadata_i
.
dat
;
rd_ack_int
<=
metadata_rack
;
when
"10"
=>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_re
<=
rd_int
;
wb_o
.
dat
<=
fmc1_adc_mezzanine_i
.
dat
;
rd_ack_int
<=
fmc1_adc_mezzanine_rack
;
when
"11"
=>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_re
<=
rd_int
;
wb_o
.
dat
<=
fmc2_adc_mezzanine_i
.
dat
;
rd_ack_int
<=
fmc2_adc_mezzanine_rack
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
end
process
;
end
syn
;
general-cores
@
75d51c0b
Subproject commit
be61ce73a43d0231e8edc2f12133b918e3d1c9e4
Subproject commit
75d51c0b92015b48b176374f9a387b2d25fa8198
svec
@
8aa8d699
Subproject commit 8aa8d699f30c3ed1d02e3aa96c00492fdb0e2051
vme64x-core
@
6abee52c
Subproject commit
1204aeca29ec3c72b6fa615976f000c664c7d152
Subproject commit
6abee52c1b5f3c2a40e202eb9f5890c05e0d7f66
hdl/syn/svec_ref_design_wr/Manifest.py
View file @
13aaea4b
...
...
@@ -9,29 +9,30 @@ syn_top = "svec_ref_fmc_adc_100Ms"
syn_project
=
syn_top
+
"_wr.xise"
syn_tool
=
"ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../../ip_cores"
files
=
[
syn_top
+
"_wr.ucf"
,
"buildinfo_pkg.vhd"
,
]
modules
=
{
"local"
:
[
"../../top/svec_ref_design"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git"
,
"git://ohwr.org/hdl-core-lib/vme64x-core.git"
,
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
],
}
fetchto
=
"../../ip_cores"
# Do not fail during hdlmake fetch
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
pass
ctrls
=
[
"bank4_64b_32b"
,
"bank5_64b_32b"
]
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd
=
(
"$(TCL_INTERPRETER) "
+
\
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
\
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
svec_base_ucf
=
[
'wr'
,
'ddr4'
,
'ddr5'
,
'led'
,
'gpio'
]
ctrls
=
[
"bank4_64b_32b"
,
"bank5_64b_32b"
]
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @
13aaea4b
This diff is collapsed.
Click to expand it.
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
View file @
13aaea4b
...
...
@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only
)
" "
Normal
"
#xilinx::project set "
Keep Hierarchy
" "
Yes
"
xilinx::project save
xilinx::project close
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
0 → 100644
View file @
13aaea4b
`define
SPEC_REF_FMC_ADC_100M_MMAP_SIZE
32768
`define
ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA
'
h2000
`define
SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define
ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE
'
h4000
`define
SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define
ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE
'
h6000
`define
SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
hdl/top/svec_ref_design/Manifest.py
View file @
13aaea4b
files
=
[
"svec_ref_fmc_adc_100Ms.vhd"
,
"
svec_carrier_csr
.vhd"
,
"
../../cheby/svec_ref_fmc_adc_100Ms_mmap
.vhd"
,
]
fetchto
=
"../../ip_cores"
modules
=
{
"local"
:
[
"../../../"
,
],
"git"
:
[
"https://ohwr.org/project/general-cores.git"
,
"https://ohwr.org/project/wr-cores.git"
,
"https://ohwr.org/project/ddr3-sp6-core.git"
,
"https://ohwr.org/project/vme64x-core.git"
,
"https://ohwr.org/project/svec.git"
,
],
}
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @
13aaea4b
This diff is collapsed.
Click to expand it.
software/drivers/Kbuild
View file @
13aaea4b
...
...
@@ -12,7 +12,7 @@ ccflags-y += -DDRV_VERSION=\"$(DRV_VERSION)\"
ccflags-y += -Wall -Werror
obj-m := fmc-adc-100m-ref-spec.o
#
obj-m += fmc-adc-100m-ref-svec.o
obj-m += fmc-adc-100m-ref-svec.o
fmc-adc-100m-ref-spec-objs := fmc-adc-100m-ref-spec-core.o
#
fmc-adc-100m-ref-svec-objs := fmc-adc-100m-ref-svec-core.o
fmc-adc-100m-ref-svec-objs := fmc-adc-100m-ref-svec-core.o
software/drivers/fmc-adc-100m-ref-svec-core.c
0 → 100644
View file @
13aaea4b
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mod_devicetable.h>
enum
ft_svec_dev_offsets
{
FT_SVEC_FA100_S1_MEM_START
=
0x00002000
,
FT_SVEC_FA100_S1_MEM_END
=
0x00003A00
,
FT_SVEC_FA100_S2_MEM_START
=
0x00004000
,
FT_SVEC_FA100_S2_MEM_END
=
0x00005A00
,
};
/* MFD devices */
enum
svec_fpga_mfd_devs_enum
{
FT_SVEC_MFD_FA100_S1
,
FT_SVEC_MFD_FA100_S2
,
};
static
struct
resource
ft_svec_fdt100_res_s1
[]
=
{
{
.
name
=
"fmc-adc-100m14b4ch-mem"
,
.
flags
=
IORESOURCE_MEM
,
.
start
=
FT_SVEC_FA100_S1_MEM_START
,
.
end
=
FT_SVEC_FA100_S1_MEM_END
,
},
{
.
name
=
"fmc-adc-100m14b4ch-irq"
,
.
flags
=
IORESOURCE_IRQ
|
IORESOURCE_IRQ_HIGHLEVEL
,
.
start
=
0
,
.
end
=
0
,
},
};
static
struct
resource
ft_svec_fdt100_res_s2
[]
=
{
{
.
name
=
"fmc-adc-100m14b4ch-mem"
,
.
flags
=
IORESOURCE_MEM
,
.
start
=
FT_SVEC_FA100_S2_MEM_START
,
.
end
=
FT_SVEC_FA100_S2_MEM_END
,
},
{
.
name
=
"fmc-adc-100m14b4ch-irq"
,
.
flags
=
IORESOURCE_IRQ
|
IORESOURCE_IRQ_HIGHLEVEL
,
.
start
=
1
,
.
end
=
1
,
},
};
static
const
struct
mfd_cell
ft_svec_mfd_devs
[]
=
{
[
FT_SVEC_MFD_FA100_S1
]
=
{
.
name
=
"adc-100m-svec"
,
.
platform_data
=
NULL
,
.
pdata_size
=
0
,
.
num_resources
=
ARRAY_SIZE
(
ft_svec_fdt100_res_s1
),
.
resources
=
ft_svec_fdt100_res_s1
,
},
[
FT_SVEC_MFD_FA100_S2
]
=
{
.
name
=
"adc-100m-svec"
,
.
platform_data
=
NULL
,
.
pdata_size
=
0
,
.
num_resources
=
ARRAY_SIZE
(
ft_svec_fdt100_res_s2
),
.
resources
=
ft_svec_fdt100_res_s2
,
},
};
static
int
ft_svec_probe
(
struct
platform_device
*
pdev
)
{
struct
resource
*
rmem
;
int
irq
;
rmem
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
if
(
!
rmem
)
{
dev_err
(
&
pdev
->
dev
,
"Missing memory resource
\n
"
);
return
-
EINVAL
;
}
irq
=
platform_get_irq
(
pdev
,
0
);
if
(
irq
<
0
)
{
dev_err
(
&
pdev
->
dev
,
"Missing IRQ number
\n
"
);
return
-
EINVAL
;
}
/*
* We know that this design uses the HTVIC IRQ controller.
* This IRQ controller has a linear mapping, so it is enough
* to give the first one as input
*/
return
mfd_add_devices
(
&
pdev
->
dev
,
PLATFORM_DEVID_AUTO
,
ft_svec_mfd_devs
,
ARRAY_SIZE
(
ft_svec_mfd_devs
),
rmem
,
irq
,
NULL
);
}
static
int
ft_svec_remove
(
struct
platform_device
*
pdev
)
{
mfd_remove_devices
(
&
pdev
->
dev
);
return
0
;
}
static
const
struct
platform_device_id
ft_svec_id_table
[]
=
{
{
.
name
=
"fmc-adc-100m-svec"
,
.
driver_data
=
0
,
},
{
.
name
=
"id:000010DC41444302"
,
.
driver_data
=
0
,
},
{
.
name
=
"id:000010dc41444302"
,
.
driver_data
=
0
,
},
{},
};
static
struct
platform_driver
ft_svec_driver
=
{
.
driver
=
{
.
name
=
"fmc-adc-100m-svec"
,
.
owner
=
THIS_MODULE
,
},
.
id_table
=
ft_svec_id_table
,
.
probe
=
ft_svec_probe
,
.
remove
=
ft_svec_remove
,
};
module_platform_driver
(
ft_svec_driver
);
MODULE_AUTHOR
(
"Federico Vaga <federico.vaga@cern.ch>"
);
MODULE_LICENSE
(
"GPL"
);
MODULE_VERSION
(
DRV_VERSION
);
MODULE_DESCRIPTION
(
"Driver for the FMC ADC 100M SVEC REF"
);
MODULE_DEVICE_TABLE
(
platform
,
ft_svec_id_table
);
MODULE_SOFTDEP
(
"pre: svec_fmc_carrier fmc-adc-100m14b4ch"
);
software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h
0 → 100644
View file @
13aaea4b
#ifndef __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
/* a ROM containing the application metadata */
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
/* FMC ADC Mezzanine slot 1 */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0x4000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
/* FMC ADC Mezzanine slot 2 */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0x6000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
struct
spec_ref_fmc_adc_100m_mmap
{
/* padding to: 2048 words */
uint32_t
__padding_0
[
2048
];
/* [0x2000]: SUBMAP a ROM containing the application metadata */
uint32_t
metadata
[
16
];
/* padding to: 4096 words */
uint32_t
__padding_1
[
2032
];
/* [0x4000]: SUBMAP FMC ADC Mezzanine slot 1 */
struct
fmc_adc_mezzanine_mmap
fmc1_adc_mezzanine
;
/* [0x6000]: SUBMAP FMC ADC Mezzanine slot 2 */
struct
fmc_adc_mezzanine_mmap
fmc2_adc_mezzanine
;
};
#endif
/* __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__ */
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