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FMC ADC 100M 14b 4cha
Commit 96563b44 authored by Tristan Gingold's avatar Tristan Gingold
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mezzanine: add pipelining in regs to relax timing.

parent 8e3c8c2b
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hdl/cheby/Makefile
View file @ 96563b44
......@@ -3,7 +3,6 @@
# SPDX-License-Identifier: CC0-1.0
SIM =../testbench/include
SW =../../software/include/hw
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
......@@ -13,8 +12,7 @@ all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@echo -e "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
--gen-consts=$(SIM)/$(@:.vhd=.v)
hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
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hdl/cheby/fmc_adc_100Ms_csr.cheby
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......@@ -12,6 +12,7 @@ memory-map:
x-hdl:
busgroup: True
iogroup: fmc_adc_100ms_csr
pipeline: wr,rd
children:
- reg:
name: ctl
......
hdl/cheby/fmc_adc_100Ms_csr.vhd
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hdl/cheby/fmc_adc_aux_trigin.vhd
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hdl/cheby/fmc_adc_aux_trigout.cheby
View file @ 96563b44
......@@ -8,7 +8,7 @@ memory-map:
description: FMC ADC aux trigger out registers
x-hdl:
busgroup: True
reg_prefix: False
reg-prefix: False
children:
- reg:
name: status
......
hdl/cheby/fmc_adc_aux_trigout.vhd
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hdl/cheby/fmc_adc_eic_regs.vhd
View file @ 96563b44
......@@ -40,7 +40,6 @@ entity fmc_adc_eic_regs is
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
fmc_adc_eic_regs_i : in t_fmc_adc_eic_regs_master_in;
fmc_adc_eic_regs_o : out t_fmc_adc_eic_regs_master_out
......@@ -48,19 +47,28 @@ entity fmc_adc_eic_regs is
end fmc_adc_eic_regs;
architecture syn of fmc_adc_eic_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal adr_int : std_logic_vector(3 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal idr_wreq : std_logic;
signal ier_wreq : std_logic;
signal isr_wreq : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(3 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(3 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
......@@ -72,7 +80,7 @@ begin
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
......@@ -83,7 +91,7 @@ begin
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
......@@ -91,105 +99,84 @@ begin
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- Process for write requests.
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
fmc_adc_eic_regs_o.idr_wr <= '0';
fmc_adc_eic_regs_o.ier_wr <= '0';
fmc_adc_eic_regs_o.isr_wr <= '0';
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
wr_ack_int <= '0';
fmc_adc_eic_regs_o.idr_wr <= '0';
fmc_adc_eic_regs_o.ier_wr <= '0';
fmc_adc_eic_regs_o.isr_wr <= '0';
case wb_i.adr(3 downto 2) is
when "00" =>
-- Register idr
fmc_adc_eic_regs_o.idr_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.idr <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "01" =>
-- Register ier
fmc_adc_eic_regs_o.ier_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.ier <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "10" =>
-- Register imr
when "11" =>
-- Register isr
fmc_adc_eic_regs_o.isr_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.isr <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => 'X');
case wb_i.adr(3 downto 2) is
when "00" =>
-- idr
rd_ack1_int <= rd_int;
when "01" =>
-- ier
rd_ack1_int <= rd_int;
when "10" =>
-- imr
reg_rdat_int <= fmc_adc_eic_regs_i.imr;
rd_ack1_int <= rd_int;
when "11" =>
-- isr
reg_rdat_int <= fmc_adc_eic_regs_i.isr;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
-- Register idr
fmc_adc_eic_regs_o.idr <= wr_dat_d0;
fmc_adc_eic_regs_o.idr_wr <= idr_wreq;
-- Register ier
fmc_adc_eic_regs_o.ier <= wr_dat_d0;
fmc_adc_eic_regs_o.ier_wr <= ier_wreq;
-- Register imr
-- Register isr
fmc_adc_eic_regs_o.isr <= wr_dat_d0;
fmc_adc_eic_regs_o.isr_wr <= isr_wreq;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0) begin
idr_wreq <= '0';
ier_wreq <= '0';
isr_wreq <= '0';
case wr_adr_d0(3 downto 2) is
when "00" =>
-- Reg idr
idr_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg ier
ier_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "10" =>
-- Reg imr
wr_ack_int <= wr_req_d0;
when "11" =>
-- Reg isr
isr_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
process (adr_int, rd_req_int, fmc_adc_eic_regs_i.imr, fmc_adc_eic_regs_i.isr) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- idr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- ier
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- imr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- isr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_dat_d0 <= (others => 'X');
case adr_int(3 downto 2) is
when "00" =>
-- Reg idr
rd_ack_d0 <= rd_req_int;
when "01" =>
-- Reg ier
rd_ack_d0 <= rd_req_int;
when "10" =>
-- Reg imr
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= fmc_adc_eic_regs_i.imr;
when "11" =>
-- Reg isr
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= fmc_adc_eic_regs_i.isr;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/cheby/fmc_adc_mezzanine_mmap.cheby
View file @ 96563b44
......@@ -9,6 +9,7 @@ memory-map:
size: 0x2000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: fmc_adc_100m_csr
......
hdl/cheby/fmc_adc_mezzanine_mmap.vhd
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hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
View file @ 96563b44
......@@ -28,8 +28,9 @@ entity spec_ref_fmc_adc_100m_mmap is
end spec_ref_fmc_adc_100m_mmap;
architecture syn of spec_ref_fmc_adc_100m_mmap is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal adr_int : std_logic_vector(14 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
......@@ -37,22 +38,29 @@ architecture syn of spec_ref_fmc_adc_100m_mmap is
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fmc_adc_mezzanine_re : std_logic;
signal fmc_adc_mezzanine_we : std_logic;
signal fmc_adc_mezzanine_wt : std_logic;
signal fmc_adc_mezzanine_rt : std_logic;
signal fmc_adc_mezzanine_tr : std_logic;
signal fmc_adc_mezzanine_wack : std_logic;
signal fmc_adc_mezzanine_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(14 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(14 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
......@@ -64,7 +72,7 @@ begin
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
......@@ -75,7 +83,7 @@ begin
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
......@@ -83,16 +91,33 @@ begin
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Assignments for submap metadata
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
......@@ -100,19 +125,21 @@ begin
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & wb_i.adr(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= (others => '1');
metadata_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wb_i.dat;
metadata_o.dat <= wr_dat_d0;
-- Assignments for submap fmc_adc_mezzanine
-- Interface fmc_adc_mezzanine
fmc_adc_mezzanine_tr <= fmc_adc_mezzanine_wt or fmc_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_mezzanine_rt <= '0';
fmc_adc_mezzanine_wt <= '0';
else
fmc_adc_mezzanine_rt <= (fmc_adc_mezzanine_rt or fmc_adc_mezzanine_re) and not fmc_adc_mezzanine_rack;
fmc_adc_mezzanine_wt <= (fmc_adc_mezzanine_wt or fmc_adc_mezzanine_we) and not fmc_adc_mezzanine_wack;
end if;
end if;
end process;
......@@ -120,75 +147,48 @@ begin
fmc_adc_mezzanine_o.stb <= fmc_adc_mezzanine_tr;
fmc_adc_mezzanine_wack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_rack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_rt;
fmc_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc_adc_mezzanine_o.sel <= (others => '1');
fmc_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & adr_int(12 downto 2)) & (1 downto 0 => '0');
fmc_adc_mezzanine_o.sel <= wr_sel_d0;
fmc_adc_mezzanine_o.we <= fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_o.dat <= wb_i.dat;
fmc_adc_mezzanine_o.dat <= wr_dat_d0;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wt <= '0';
fmc_adc_mezzanine_wt <= '0';
else
wr_ack_int <= '0';
metadata_wt <= '0';
fmc_adc_mezzanine_wt <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_wt <= (metadata_wt or wr_int) and not metadata_wack;
wr_ack_int <= metadata_wack;
when "10" =>
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_wt <= (fmc_adc_mezzanine_wt or wr_int) and not fmc_adc_mezzanine_wack;
wr_ack_int <= fmc_adc_mezzanine_wack;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => 'X');
case wb_i.adr(14 downto 13) is
when "01" =>
when "10" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
process (wr_adr_d0, wr_req_d0, metadata_wack, fmc_adc_mezzanine_wack) begin
metadata_we <= '0';
fmc_adc_mezzanine_we <= '0';
case wr_adr_d0(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_int <= metadata_wack;
when "10" =>
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_we <= wr_req_d0;
wr_ack_int <= fmc_adc_mezzanine_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_i.dat, metadata_rack, metadata_rt, rd_int, fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack, fmc_adc_mezzanine_rt) begin
process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
fmc_adc_mezzanine_re <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
case adr_int(14 downto 13) is
when "01" =>
-- Submap metadata
metadata_re <= rd_int;
wb_o.dat <= metadata_i.dat;
rd_ack_int <= metadata_rack;
when "10" =>
metadata_re <= rd_req_int;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "10" =>
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_re <= rd_int;
wb_o.dat <= fmc_adc_mezzanine_i.dat;
rd_ack_int <= fmc_adc_mezzanine_rack;
fmc_adc_mezzanine_re <= rd_req_int;
rd_dat_d0 <= fmc_adc_mezzanine_i.dat;
rd_ack_d0 <= fmc_adc_mezzanine_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
View file @ 96563b44
......@@ -9,6 +9,7 @@ memory-map:
size: 0x8000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: metadata
......
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
View file @ 96563b44
This diff is collapsed.
hdl/cheby/timetag_core_regs.vhd
View file @ 96563b44
This diff is collapsed.
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 96563b44
......@@ -274,6 +274,8 @@ architecture rtl of fmc_adc_100Ms_core is
signal dpram_addrb_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_dout : std_logic_vector(63 downto 0);
signal dpram_valid : std_logic;
signal dpram_valid_d1 : std_logic;
signal dpram_valid_d2 : std_logic;
signal dpram_valid_t : std_logic;
signal dpram0_dina : std_logic_vector(63 downto 0);
......@@ -300,7 +302,6 @@ architecture rtl of fmc_adc_100Ms_core is
-- RAM address counter
signal ram_addr_cnt : unsigned(28 downto 0);
signal trig_addr : std_logic_vector(31 downto 0);
signal mem_ovr : std_logic;
-- LEDs
signal trig_led : std_logic;
......@@ -541,10 +542,10 @@ begin
if rising_edge(sys_clk_i) then
gpio_si570_oe_o <= csr_regout.ctl_fmc_clk_oe;
gpio_dac_clr_n_o <= csr_regout.ctl_offset_dac_clr_n;
gpio_ssr_ch1_o <= channel_regout(1).ctl_ssr;
gpio_ssr_ch2_o <= channel_regout(2).ctl_ssr;
gpio_ssr_ch3_o <= channel_regout(3).ctl_ssr;
gpio_ssr_ch4_o <= channel_regout(4).ctl_ssr;
gpio_ssr_ch1_o <= channel_regout(1).ctl_ssr;
gpio_ssr_ch2_o <= channel_regout(2).ctl_ssr;
gpio_ssr_ch3_o <= channel_regout(3).ctl_ssr;
gpio_ssr_ch4_o <= channel_regout(4).ctl_ssr;
end if;
end process p_delay_gpio_ssr;
......@@ -789,12 +790,14 @@ begin
ext_trig_delay_bsy <= '0';
else
if ext_trig = '1' and ext_trig_delay_bsy = '0' then
-- Start counter
ext_trig_delay_cnt <= unsigned(ext_trig_delay);
ext_trig_delay_bsy <= '1';
elsif ext_trig_delay_cnt /= 0 then
-- Count
ext_trig_delay_cnt <= ext_trig_delay_cnt - 1;
else
-- when counter reaches zero
-- When counter reaches zero
ext_trig_delay_bsy <= '0';
end if;
end if;
......@@ -984,7 +987,7 @@ begin
downsample_cnt <= to_unsigned(1, downsample_cnt'length);
downsample_en <= '0';
else
if downsample_cnt = to_unsigned(0, downsample_cnt'length) then
if downsample_cnt = 0 then
if downsample_factor /= X"00000000" then
downsample_cnt <= unsigned(downsample_factor) - 1;
end if;
......@@ -1396,23 +1399,37 @@ begin
dpram_addra_trig <= dpram_addra_cnt;
end if;
if post_trig_done = '1' then
dpram_addra_post_done <= dpram_addra_cnt;
-- reads 2 extra addresses -> trigger time-tag
dpram_addra_post_done <= dpram_addra_cnt + 2;
end if;
end if;
end if;
end process p_dpram_addra_cnt;
-- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram1_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram0_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '0' else '0';
dpram1_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '1' else '0';
p_dpram_inputs: process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
dpram0_wea <= '0';
dpram1_wea <= '1';
else
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
if acq_in_trig_tag = '0' then
dpram0_dina <= sync_fifo_dout(63 downto 0);
dpram1_dina <= sync_fifo_dout(63 downto 0);
else
dpram0_dina <= trig_tag_data;
dpram1_dina <= trig_tag_data;
end if;
dpram0_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
and not multishot_buffer_sel;
dpram1_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
and multishot_buffer_sel;
end if;
end if;
end process;
-- DPRAMs
cmp_multishot_dpram0 : generic_dpram
......@@ -1475,25 +1492,44 @@ begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_valid_t <= '0';
dpram_valid <= '0';
else
if trig_tag_done = '1' then
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_DPRAM_DEPTH-1 downto 0));
dpram_valid_t <= '1';
elsif (dpram_addrb_cnt = dpram_addra_post_done + 2) then -- reads 2 extra addresses -> trigger time-tag
elsif dpram_addrb_cnt = dpram_addra_post_done then
dpram_valid_t <= '0';
else
dpram_addrb_cnt <= dpram_addrb_cnt + 1;
end if;
dpram_valid <= dpram_valid_t;
end if;
end if;
end process p_dpram_addrb_cnt;
-- DPRAM output mux
dpram_dout <= dpram0_doutb when multishot_buffer_sel = '1' else dpram1_doutb;
dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
p_dpram_valid : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_valid <= '0';
dpram_valid_d1 <= '0';
dpram_valid_d2 <= '0';
else
dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
-- dpram_valid is delayed by 2 cycles from dpram_valid_t.
-- 1 for the dpram access, the second for the pipeline here.
dpram_valid_d1 <= dpram_valid_t;
dpram_valid_d2 <= dpram_valid_d1;
dpram_valid <= dpram_valid_d2;
if multishot_buffer_sel = '1' then
dpram_dout <= dpram0_doutb;
else
dpram_dout <= dpram1_doutb;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Flow control FIFO for data to DDR
......@@ -1585,11 +1621,7 @@ begin
end if;
end process p_ram_addr_cnt;
with acq_fsm_state select
wb_ddr_master_o.cyc <=
dpram_valid or not wb_ddr_fifo_empty when "001",
'1' when others;
wb_ddr_master_o.cyc <= dpram_valid or not wb_ddr_fifo_empty when acq_fsm_state = "001" else '1';
wb_ddr_master_o.stb <= not wb_ddr_fifo_empty;
-- Convert to 32-bit word addressing for Wishbone
wb_ddr_master_o.adr <= "00" & std_logic_vector(ram_addr_cnt) & "0";
......@@ -1703,12 +1735,12 @@ begin
trigout_trig <= f_reduce_or (trigout_triggers);
-- Acquisition trigger delayed pulse
p_acq_end : process (sys_clk_i)
p_acq_trig : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
acq_trig_d <= acq_trig;
end if;
end process p_acq_end;
end process p_acq_trig;
trigout_fifo_wr <= trigout_trig and not trigout_fifo_full and acq_trig_d;
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 96563b44
......@@ -139,14 +139,11 @@ architecture rtl of fmc_adc_mezzanine is
-- Signals declaration
------------------------------------------------------------------------------
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal wb_csr_out : t_wishbone_slave_in;
signal wb_csr_in : t_wishbone_slave_out;
......@@ -205,24 +202,12 @@ begin
master_i => wb_csr_in,
master_o => wb_csr_out);
-- Additional register to help timing
cmp_xwb_register : xwb_register
generic map (
g_WB_MODE => PIPELINED)
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
slave_i => wb_csr_out,
slave_o => wb_csr_in,
master_i => cnx_master_in,
master_o => cnx_master_out);
cmp_crossbar : entity work.fmc_adc_mezzanine_mmap
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
wb_i => cnx_master_out,
wb_o => cnx_master_in,
wb_i => wb_csr_out,
wb_o => wb_csr_in,
fmc_adc_100m_csr_i => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
fmc_adc_100m_csr_o => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
fmc_adc_eic_i => cnx_slave_out(c_WB_SLAVE_FMC_EIC),
......@@ -317,7 +302,7 @@ begin
-- ADC core control and status
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
cmp_fmc_adc_100Ms_core : entity work.fmc_adc_100Ms_core
generic map (
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
g_SPARTAN6_USE_PLL => g_SPARTAN6_USE_PLL,
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 96563b44
......@@ -641,7 +641,7 @@ begin -- architecture arch
d_i => fmc_acq_trig(I),
q_o => fmc_acq_trig_sync(I));
p_fmc_acq_led: process (fmc_acq_cfg_ok_sync) is
p_fmc_acq_led: process (fmc_acq_cfg_ok_sync, fmc_acq_trig_sync) is
begin
if fmc_acq_cfg_ok_sync(I) = '0' then
fmc_acq_led(I) <= c_LED_RED;
......
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