Past due
Milestone
expired on Sep 30, 2019
V5.0 gateware release
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
3
Completed Issues (closed)
18
- hdl - Replace glitch filter with dual threshold FSM
- hdl - Review and sanitize reset logic
- hdl - Trim unused clock signals
- Add White Rabbit support
- Replace "decimation" with "under-sampling"
- Add "trigger on time" functionality
- Add option to tag based on WR time
- Add extra trigger input from FPGA logic
- Implement a basic WR trigger message
- hdl - switch to 125MHz clock source
- gateware manual: wrong data format reported for channel status registers
- Replace hardware trigger enable logic
- Update testbench
- Update Gennum core to address critical freeze issue
- Misalignment of external trigger wrt data
- Add correct delays to all trigger sources
- Wrong sampling clock freqency in the Xilinx constraints
- doc - fix formula for calculating the corrected DAC value