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FMC ADC 100M 14b 4cha - Gateware
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  • FMC ADC 100M 14b 4cha - Gateware
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  • V5.0 gateware release

Past due
Milestone expired on Sep 30, 2019

V5.0 gateware release

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  • Issues 21
  • Merge Requests 0
  • Participants 1
  • Labels 2
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
3
  • Account for trigger sample in post-trigger samples
    #23 feature
  • Cannot use last DPRAM sample
    #22 bug
  • Expose more info in the status and/or interrupt registers
    #21 feature
Completed Issues (closed)
18
  • hdl - Replace glitch filter with dual threshold FSM
    #31 feature
  • hdl - Review and sanitize reset logic
    #30 bug
  • hdl - Trim unused clock signals
    #29 bug
  • Add White Rabbit support
    #26 feature
  • Replace "decimation" with "under-sampling"
    #25 feature
  • Add "trigger on time" functionality
    #15 feature
  • Add option to tag based on WR time
    #14 feature
  • Add extra trigger input from FPGA logic
    #13 feature
  • Implement a basic WR trigger message
    #12 feature
  • hdl - switch to 125MHz clock source
    #10 feature
  • gateware manual: wrong data format reported for channel status registers
    #9 bug
  • Replace hardware trigger enable logic
    #8 feature
  • Update testbench
    #7 feature
  • Update Gennum core to address critical freeze issue
    #5 bug
  • Misalignment of external trigger wrt data
    #4 bug
  • Add correct delays to all trigger sources
    #3 bug
  • Wrong sampling clock freqency in the Xilinx constraints
    #2 bug
  • doc - fix formula for calculating the corrected DAC value
    #1 bug
85% complete
85%
Start date
No start date
Until
Sep 30 2019
Due date
Sep 30, 2019 (Past due)
21
Issues 21 New issue
Open: 3 Closed: 18
Time tracking
0
Merge requests 0
Open: 0 Closed: 0 Merged: 0
Reference: project/fmc-adc-100m14b4cha-gw%"V5.0 gateware release"