This has been mentioned already in Section 7 (Missing features and improvements) of the Gateware manual v4.0.

Several problematic sequential processes have been already identified within the Gateware.

Potentially problematic reset strategies include the main power-up reset process in the top-level SPEC design, as well as the various asynchronous resets in the FMC ADC core block.

The whole reset strategy should be reviewed and, if necessary, amended.

These changes (if any) will be internal to the Gateware and will thus not break backwards software compatibility.