A couple of clock signals described in the VHDL code are not used anywhere in the design.

Examples include the L_CLK top-level differential pair on the SPEC board, which is buffered via a IBUFDS element and then left unused, and a 250MHz PLL clock output which is buffered via a BUFG element and then left unused. This list is not exhaustive.

These changes (if any) will be internal to the Gateware and will thus not break backwards software compatibility.