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FMC ADC 100M 14b 4cha - Gateware
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Opened Feb 08, 2016 by Dimitris Lampridis@dlampridis
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hdl - Trim unused clock signals

A couple of clock signals described in the VHDL code are not used anywhere in the design.

Examples include the L_CLK top-level differential pair on the SPEC board, which is buffered via a IBUFDS element and then left unused, and a 250MHz PLL clock output which is buffered via a BUFG element and then left unused. This list is not exhaustive.

These changes (if any) will be internal to the Gateware and will thus not break backwards software compatibility.

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Reference: project/fmc-adc-100m14b4cha-gw#29