As already explained in #4 (closed), all trigger sources (except the internal threshold triggers) should be delayed to compensate for the time it takes to sample, digitize and deliver the ADC data to the FPGA.

For the external trigger it has been calculated that we need 5 delay cycles for proper alignment.

We need to calculate the delays for time and software triggers as well.

For time triggers, it will be much easier to do it with White Rabbit in place. See also #15 (closed) and #26 (closed).