Wrong sampling clock freqency in the Xilinx constraints
The serialized ADC sampling clock is defined in the Xilinx constraints file as having a 2ns period. When propagated through the FPGA PLLs this results in a 125MHz sampling clock.
Indeed, the ADC datasheet states that for two-lane, 16-bit data, the "length" of each bit is 1/(8*Fsampling), or 1.25ns. Given the fact that the stream is DDR, the serial clock frequency will be double that, or 2.5ns.
When the serial clock is set to 2.5ns in the constraints, the propagated sampling clock is correctly calculated as 100MHz.
Using 2ns instead of 2.5ns (and therefore also 125MHz instead of 100MHz), can generate HOLD timing violations.