Open
Milestone
v3
Unstarted Issues (open and unassigned)
1
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
68
- Sch validation returns some warnings on Harness Types
- PS_POR_B connected to PL as well as PS?
- Sysmon reports different temperature of the SoC than MAX6639
- connect unused VCCO to any voltage
- I2C SW RST - discrete open collector suppression
- Some polygons have unnecessary extensions
- Silkscreen: rename EDA-04514-V3
- Cpcis_connectors: naming of MGT lanes
- no ERC markers on some assigned pins
- Bank 502 is powered from P3V3, but the label says 1.8V
- update Copyright notice
- LAN8831 power cycle signal (PME_N) to become active high
- IRPS5401 BOOT_A/B/C/D coupling to PHASE_A/B/C/D - double check capacitor value
- Remove IC57 - PL watchdog
- relocate ports and net labels, change fonts, so underscores aren't hidden by wires and busses
- harmonise the netnaming convention
- polarity of OVERTHERM
- move stand alone LDOs to "LDOs" sheet
- rename P5VREG to P5V_REG
- something odd with the footprint of TDA21535
- 12V "oring" diode with 5V on IC25
- Random numbering of MGT_CLKREF
- Move CPCIS_I2C to i2c_mux
- not all CHASSIS holes are connected together
- SI5341B power supply decoupling
- 48MHz quartz layout
- minor schematics bugs
- FMC.LA0 and FMC.LA18 are not connected to CC pins
- Tie unused MGTRREF_L and MGTAVTTRCAL_L to GND
- MAGJACK setting in the PHY needs to be double-checked.
- remove PS_POR_B connection from PL I/O bank
- SERVMOD is missing pull-up OR PRESENCE DETECT function is absent?
- unify LED forward shunts resistors to reduce the BoM
- RGMII_EN doesn't need a pull up
- single / multi port mode(0) should be set to a value
- LAN8331 power scheme should match reference design
- consider using spare pin of D12 for SDIO_DETECT
- PCB version pull down resistors should be 0R
- USB JTAG TRST isn't isolated from 3V3
- omitted constraints on MGT signals to FMC connector
- MODE1,2 are swapped on bank503
- Heatsink collide with power connector
- DDR4-PL.CK_P connected to N-side
- fmc-connector: fuse on P12V
- Ethernet_PHY_RJ45: missing GPIO to power cycle circuit connection
- Ethernet_PHY_RJ45: missing 10uF cap on VDDIO
- PSU_ALERT pin left unconnected
- PCB Version resistors set to 4 instead of 3
- SI53312-B-GM reduction
- MGT connectivity
- PS QSPI max frequency fails in x4 mode
- Obsolete components
- Reconfiguration of I2C buses connections
- mmc size incremented
- SD Card reader
- improve qspi memories
- Replace front pannel microUSB connector with USB-C
- Replace CP2105 with FT4232H
- Verify with current v2 if we need back-drilling on FMC transceiver lines.
- Increase PS DDR to 8 GB
- Replace SFP (J5) with RJ-45 connector and Ethernet PHY with Wake-on-LAN and pattern matching.
- Replace XCZU7CG-1FFVF1517E with XCZU17EG-1FFVC1760E
- TDA21240 is obsolete
- replace C284 with 3x 100uF capacitors to avoid P1V2 spurious shutdown
- update Power sequencing note in power-supply-2.SchDoc
- IRPS5401 IC30 configuration
- PUDC_B is connected to 1V8 instead of 1V8_AUX
- fpga-ps-mio: PESD3V3S4UD (D11, D12) has too high capacitance which disrupts SDIO clock making the board unable to boot from SD card