LAN8831 power cycle signal (PME_N) to become active high
On the effort to match the signal polarity on the pin used to output the Power Management Event (PME_N
) flag (from the LAN8831 PHY chip) and its original function, the polarity of PME_N
will be programmatically changed from active-low to active-high. This is done to avoid eventual unwanted trigger of the crate power cycling timer by the active-low signal. This can happen on the short interval where the LAN8831 chip is powered on, but not configured by the FSBL driver.
In terms of schematics, the PHY_GPIO_RST_N
signal should be considered active-high (and thus renamed PHY_GPIO_RST
). To implement this behavior, I suggest the removal of R15
and T9
, and changing R14
from being a pull-up resistor to a pull-down resistor. This will not be a problem considering the output buffer of the GPIO pin will be set to push-pull (and not open-drain).