DI/OT Zynq Ultrascale-based System Board with White Rabbit support
Project description
The DI/OT System Board is one of the main components of the Distributed I/O Tier project ecosystem. It is mechanically and electrically compliant with the Compact PCI Serial standard (CPCI-S.0). As part of the integration with the Sinara ecosystem for quantum physics experiments, DI/OT System Board will have two executions to serve both CERN and Sinara requirements.
The DI/OT System Board controls the whole DI/OT crate, communicating with up to 8 Peripheral Boards and higher layers of the control system using White Rabbit, Gigabit Ethernet or any other industrial fieldbus.
Main features
- Xilinx Zynq UltraScale+ SoC (XCZU7CG-1FFVF1517E)
- 4GB DDR4 memory with ECC for Processing System (ARM processor)
- 1GB DDR4 memory for FPGA Programmable Logic
- 4GB eMMC and 64MB QSPI Flash
- MicroSD card slot
- SFP for 1/10Gb Ethernet and White Rabbit support
- FMC slot with high pin count (HPC) connector
- Vadj 1.8V
- LA bank connected to FPGA (HA, HB banks not available)
- 8 MGT Tx/Rx lanes connected to FPGA GTH
- DI/OT backplane connectors
- 287 FPGA I/Os
- 8 MGTs (1 per Peripheral Slot)
- Low skew clock distribution from programmable Si5341 generator
- DI/OT crate control/monitoring I/Os
Related links and documents
Contacts
- Greg Daniluk - CERN
Status
| Date | Event |
|---|---|
| Jul-2019 | Project starts, gathering specification |
| Jan-2020 | First version of schematics reviewed |
| Apr-2020 | Final version of schematics reviewed and approved |
| Sep-2020 | v1.0 of layout reviewed and approved, SI/PI simulations ongoing |
| 21-10-2020 | Order for three prototypes placed |
| 02-12-2020 | Design v1.0 ready, including fixes after SI/PI simulations, prototypes production starting |
| 31-03-2021 | 3 prototypes received |
| 07-07-2021 | Prototypes validated, after fixing minor issues we're going for the first production batch |
| 23-07-2021 | v2.0 being designed and will be reviewed by CERN's design office |
| 08-12-2021 | v2.0 boards being produced, design provided to CERN's design office |
| 24-02-2022 | 20 System Boards v2.0 delivered to CERN |