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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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Projects / PPSi
GNU Lesser General Public License v2.1 onlyA Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.
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Radiation-tolerant AC/DC power supply unit (PSU). In: 230VAC, 50Hz, Out: +12V, 8.33A (100W) and +5V, 2A (10W). Possibility for redundancy. The design is CompactPCI compatible. Part of DIOT project.
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Training project to learn about Power Delivery Network measurements and simulations. With a PDN usually the power distribution on a PCB is meant. This project describes a PCB with additional connectors to measure the power distribution quality. More info at the Wiki page
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FMC 4 channel Serial link transceiver with differential LEMO connectors. Differential signalling with Vh=3.3V and Vl=1.7V. More info at the Wiki page
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VME projects are sub-projects of this ohwr project. See all sub-projects for more information.
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White Rabbit Switch WRS-3/18 (hardware version 3.4) with modified SCB prepared for the low-jitter daughterboard and modified backplane. Commercially available. More info at the Wiki page
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PUMA (Plataforma Utilizada para el Muestreo de Arapuca) is a multi-channel digitizer designed to instrument the photon detection system for the DUNE Photon Detection System. However, it may be useful for other applications that require 40 - 64 channels of 14-bit digitzier sampling at 10MSample/s - 65MSample/s. PUMA is based on the digitizer designed for the SoLiD short baseline reactor neutrino detector. It is designed to be connected to external signal conditioning modules, which are controlled by I2C. More info at the Wiki page
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Projects / Euro ADC 65M 14b 40cha gw PUMA-gw
Apache License 2.0Updated -
Projects / Euro ADC 65M 14b 40cha hw PUMA-hw
CERN Open Hardware Licence v1.2Updated -
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This project focuses on performing with high precision the core WR PTP calculations in fixed-point arithmetic. This will ensure uniform input parameters, code and precision across all WR implementations.
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This project hosts compliance tests dedicated for WR devices and based on the ATTEST framework available from Veryx Technologies. To use the material available in this project, the ATTEST framework needs to be purchased.
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COM Express based PXIe system controller. COM Express Compact Pin-out type 6, 16-lane PCIe GEN3. PXIe trigger line on front-panel. More info at the Wiki page
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Projects / VHDL macro libraries for Microsemi ProASIC3
GNU Affero General Public License v3.0This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.
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