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A low cost, low complexity FMC carrier based on Xilinx Artix-7

FMC VHDCI is a simple breakout board that connects signals from an Low Pin Count (LPC) FMC connector to an VHDCI connector. The signals are not buffered. More info at the Wiki page

PC/104 OneBank Carrier for SoC Modules. The EMC2-DP is a PCIe/104 OneBank Carrier for a Trenz compatible SoC Module and has expansion for a VITA57.1 FMC LPC I/O board and also has I/O pins, using a 100-way Samtec RazorBeam connectors system. Board developed with EU funding on the Artemis EMC2 project. More info at the Wiki page

YAM is a micro-controller core aiming at simple yet fast IO sequencing with integer processing capabilities. YAM parameters may be assigned to fit many applications. The data width is scalable from 8 to any value (like 32 or larger) size.

FMC prototype board fmc-prt-lpc is providing means to develop FMC systems for later integration to standard FMC Low-Pin Count form factor. Breadboard area connecting LPC pins. More info at the Wiki page

A VME rear transition module providing fibre-optic and electrical (RS485) inputs and outputs. Uses the CONV-TTL-RS485 as front-module. More info at the Wiki page

High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.

For more information, see the wiki

PCIe to VME bridge. More info at the Wiki page

The High Performance WR Receiver module is an MTCA eRTM (slots 14-15) WR receiver with redundant uplinks, providing a variety of ultra-low jitter clock signals.

More info at the Wiki page

A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page

VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page

Fanless version of the White Rabbit Switch WRS-3/18 (hardware version 3.4) with the low-jitter daughterboard integrated. More info at the Wiki page

A plug&play mini-module for flexible White Rabbit integration. The SFP fibre-optic module should be implemented on the carrier board. More info at the Wiki page

Radiation tolerant LED luminaires. Currently in production with two manufacturers. More info at the Wiki page

The CTR FMC is an FMC card that can be used, in conjunction with the Simple PCIe FMC carrier (SPEC), to design a General Machine Timing (GMT) Receiver. More info at the Wiki page

A radiation-tolerant digital I/O module with sixteen 24 Volt optically isolated inputs and outputs. 3U module with AirMax backplane connector for DIOT crate.

The OPT ADC 10k 32b 1cha is a single channel 10kSPS 32 bit ADC card in the format defined by the CERN TE-EPC group for use with the Function Generator Controller (FGC 3.2) . It is also known under the name HPM7177.

Intel Arria V based VME64x carrier for one FMC+ mezzanine with six SFP connectors, DDR3 memory and clocking resources to support White Rabbit. For more details please refer to the wiki pages.

This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification

LIST is a trigger distribution system based on White Rabbit. It can receive a trigger from a “cloud” of devices and distribute it to all relevant devices to for example freeze their acquisition buffers. The latency between reception and transmission of a trigger is done with a low and notably fixed latency, with an accuracy of better than 1 ns. The hardware of the LIST nodes is based on the SVEC FMC carrier equipped with a FMC TDC mezzanine and a Fine Delay mezzanine. More info at the Wiki page