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Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.
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A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
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Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.
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DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
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A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.
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CompactRIO module with White Rabbit functionality. LabVIEW support, front-panel connector with 10 I/O lines.
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Production and functional tests for Conv TTL Blocking. More info at the Wiki page
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Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page
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Common gateware for the different level conversion circuits.
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Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.
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A low cost, low complexity FMC carrier based on Xilinx Artix-7
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Projects / AsyncArt
GNU Lesser General Public License v2.1 onlyThe AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.
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VHDL core for absolute position encoders (SSI, BISS, ENDAT).
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TiCkS is a flexible White Rabbit based time-stamping board. It is based on the SPEC board developed for the CTA collaboration. It provides an interface to a CTA camera (Inputs: Read-out Trigger signals, Busy Trigger), (Outputs: PPS signal , 10MHz clock, External trigger signal).
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Projects / FMC High-Voltage supply - fmc-hv-2ch
GNU Lesser General Public License v2.1 onlyFMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page
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Mathieu Saccani / VME64x core - msaccani
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
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Production and functional tests for PXIe controller COM Express based. More info at the Wiki page
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