HydRA - a radiation-tolerant SoC
Description
HydRA, acronym of Hydra-like Resilient Architecture, is a radiation-tolerant SoC designed to operate up to 500 Gy TID. It is intended to work on any FPGA with sufficient resources, and its initial intended application is in the DI/OT ecosystem for radiation-tolerant electronics.
Main Features
- Gateware
- RISC-V CPU: uRV-core
- Clock speed: 50 MHz
- ROM for code: 96 kByte
- RAM: 64 kByte
- 2 x Ethernet NIC with low-latency L2 packet switching
- SPI
- Watchdog
- Provided Software
- User example
- Powerlink stack
Documentation
- Presentation on the use of Hydra for implementing a rad-tol Powerlink node
- Users
Contacts
- Tristan Gingold - CERN
- Mattia Rizzi - ex CERN. Started the development
Project Status
| Date | Event |
|---|---|
| Feb-2018 | Start of project, R2E research for rad-tol Ethernet Phy |
| Aug-2018 | First CHARM irradiation of RISC-V |
| Oct-2018 | CHARM irradiation of RISC-V with ECC-protected memory |
| Nov-2018 | Hydra development status and tests result presentation at 29th RADWG meeting |
| Mar-2019 | First version of shrunk-down OpenPowerlink running in Hydra with partial triplication |
| May-2019 | Ethernet loopback radiation testing in PSI |
| Jul-2019 | Hydra includes fully triplicated RISC-V (at 50MHz), logic for the recovery from misaligned CPUs, SECDED ECC |
| Sep-2019 | OpenPowerlink stack runs on triplicated RISC-V |
| Dec-2019 | Ethernet PHY selection concluded on KSZ8081 |
| Jul-2020 | PSI radiation test of Hydra - only 2 uncorrectable memory errors up to 500Gy |
| Dec-2020 | Hydra performance presented to R2E. TID: 500Gy, cross-section: ~3e-12 |
| Nov-2021 | Project will be consolidated. Not yet ready to be offered as a block. |
9 November 2021