Explore projects
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High-resolution frequency/phase-microstepper for timing laboratories. More info at the Wiki page
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High precision, ultra stable Oven Controlled Crystal Oscillator (OCXO) suitable for the Metrology purposes in a 19" format. Can be used to upgrade the performance of the SPEC7.
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Zynq CarrIer for Timing sYstems based on radiofrequency over White Rabbit, aka CITY.
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Projects / AIDA-2020 TLU - Gateware
GNU General Public License v3.0 or laterFPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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This is a PCB-design + Arduino firmware for an Ethernet-controlled 1:8 RF-multiplexer. It allows selecting as output one of eight input-channels, as commonly used e.g. in timing-laboratories when one wants to measure many RF-sources (clock outputs like 1PPS or 10MHz) with a single instrument (frequency or time-interval counter). The design is for two independent MUX-boards to fit in a 1U 19” rack enclosure. For more information, see the wiki
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A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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A White Rabbit Timing Receiver in AMC (Advanced Mezzanine Card, AdvancedMC) format. More info at the Wiki page
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A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
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Production and functional tests for fmc-dac-600m-12b-1cha-dds
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A White Rabbit Timing Receiver in PMC (PCI Mezzanine Card) format. More info at the Wiki page
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Projects / Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
MIT LicenseThe CUTE-WR-DP is the enhanced version of CUTE-WR with dual WR ports. You can use it as the normal WR node with one SFP port. CUTE-WR-DP can work in chain to support cascade topology. In future, CUTE-WR-DP could support dualport redundancy function for high reliable application. More info at the Wiki page
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The FmcAdc1G8b2cha is a 2 channel 1GSPS 8 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a Low Pin-Count (LPC) connector.
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FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page
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A meta project used to discuss and present information about Open Hardware and related subjects. More info at the Wiki page More info about the CERN Open Hardware licence More info about the OHR.org site support
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OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs. More info at the Wiki page
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FMCprojects shows the FMC Mezzanine and Carrier boards that are developed in the Open Hardware Repository context. Furthermore it gives useful data helping you to design modules complying to this VITA 57.1 standard. This actually is not a hardware project, but is there to help you find your way in the FMC standard and shows you which FMC Mezzanines and Carriers are being developed in the context of the Open Hardware project.
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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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This project covers the hardware development of version 4 of the White Rabbit switch (WRS-v4). More info at the Wiki page
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