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A Time to Digital Converter core for Spartan 6 FPGAs.

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page

Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

Hydra is a RISC-V based radiation-tolerant SoC designed to operate up to 500 Gy TID. See the wiki for more details.

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.

Production and functional tests for Conv TTL RS485

Test. May be deleted.

The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

A low cost, low complexity FMC carrier based on Xilinx Artix-7

Production and functional tests for the MasterFIP.

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

Gateware (HDL design) for Conv TTL RS485

PCIe to VME bridge. More info at the Wiki page