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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit eef777b5 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Marek Gumiński
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[PSU] simulation driver for PSU

parent 5fdc7ad8
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Showing with 141 additions and 3 deletions
sim/regs/psu_regs.v 0 → 100644
View file @ eef777b5
`define ADDR_PSU_PCR 4'h0
`define PSU_PCR_PSU_ENA_OFFSET 0
`define PSU_PCR_PSU_ENA 32'h00000001
`define PSU_PCR_IGNORE_RX_PID_OFFSET 1
`define PSU_PCR_IGNORE_RX_PID 32'h00000002
`define PSU_PCR_INJ_PRIO_OFFSET 8
`define PSU_PCR_INJ_PRIO 32'h00000700
`define PSU_PCR_HOLDOVER_CLK_CLASS_OFFSET 16
`define PSU_PCR_HOLDOVER_CLK_CLASS 32'hffff0000
`define ADDR_PSU_RXPM 4'h4
`define PSU_RXPM_PORT_MASK_OFFSET 0
`define PSU_RXPM_PORT_MASK 32'hffffffff
`define ADDR_PSU_TXPM 4'h8
`define PSU_TXPM_PORT_MASK_OFFSET 0
`define PSU_TXPM_PORT_MASK 32'hffffffff
`define ADDR_PSU_PTD 4'hc
`define PSU_PTD_DBG_HOLDOVER_ON_OFFSET 0
`define PSU_PTD_DBG_HOLDOVER_ON 32'h00000001
`define PSU_PTD_TX_RAM_RD_ENA_OFFSET 1
`define PSU_PTD_TX_RAM_RD_ENA 32'h00000002
`define PSU_PTD_TX_RAM_RD_ADR_OFFSET 4
`define PSU_PTD_TX_RAM_RD_ADR 32'h00003ff0
`define PSU_PTD_TX_RAM_RD_DAT_OFFSET 14
`define PSU_PTD_TX_RAM_RD_DAT 32'hffffc000
sim/simdrv_psu.svh 0 → 100644
View file @ eef777b5
`ifndef __SIMDRV_WR_PSU
`define __SIMDRV_WR_PSU 1
`timescale 1ns/1ps
`include "simdrv_defs.svh"
`include "regs/psu_regs.v"
class CSimDrv_PSU;
protected CBusAccessor m_acc;
protected uint64_t m_base;
function new(CBusAccessor acc, uint64_t base, bit dbg=0);
m_acc = acc;
m_base = base;
endfunction // new
task init(bit[2:0] inj_prio, bit[15:0] holdover_clk_class, bit ignore_rx_port_id,
bit[31:0] rx_mask, bit[31:0] tx_mask );
m_acc.write(m_base + `ADDR_PSU_PCR,
(holdover_clk_class << `PSU_PCR_HOLDOVER_CLK_CLASS_OFFSET) & `PSU_PCR_HOLDOVER_CLK_CLASS |
(inj_prio << `PSU_PCR_INJ_PRIO_OFFSET ) & `PSU_PCR_INJ_PRIO |
(ignore_rx_port_id << `PSU_PCR_IGNORE_RX_PID_OFFSET ) & `PSU_PCR_IGNORE_RX_PID);
m_acc.write(m_base + `ADDR_PSU_RXPM, rx_mask);
m_acc.write(m_base + `ADDR_PSU_TXPM, tx_mask);
endtask;
task enable(bit onoff);
uint64_t tmp;
m_acc.read(m_base + `ADDR_PSU_PCR, tmp, 4);
if(onoff)
tmp = tmp | `PSU_PCR_PSU_ENA;
else
tmp = tmp & ~`PSU_PCR_PSU_ENA;
m_acc.write(m_base + `ADDR_PSU_PCR, tmp);
endtask;
task tx_port_enable(int port_id, bit onoff);
uint64_t tmp;
m_acc.read(m_base + `ADDR_PSU_TXPM, tmp, 4);
if(onoff)
tmp = tmp | (1 << port_id);
else
tmp = tmp & ~(1 << port_id);
m_acc.write(m_base + `ADDR_PSU_TXPM, tmp);
endtask;
task rx_port_enable(int port_id, bit onoff);
uint64_t tmp;
m_acc.read(m_base + `ADDR_PSU_RXPM, tmp, 4);
if(onoff)
tmp = tmp | (1 << port_id);
else
tmp = tmp & ~(1 << port_id);
m_acc.write(m_base + `ADDR_PSU_RXPM, tmp);
endtask;
task dbg_holdover(onoff);
if(onoff)
m_acc.write(m_base + `ADDR_PSU_PTD, `PSU_PTD_DBG_HOLDOVER_ON);
else
m_acc.write(m_base + `ADDR_PSU_PTD, 'h0000);
endtask;
task dbg_dump_tx_ram();
uint64_t i;
uint64_t tmp;
for(i=0;i<1024;i++)
begin
m_acc.write(m_base + `ADDR_PSU_PTD,
`PSU_PTD_TX_RAM_RD_ENA |
(i << `PSU_PTD_TX_RAM_RD_ADR_OFFSET) & `PSU_PTD_TX_RAM_RD_ADR);
m_acc.read(m_base + `ADDR_PSU_PTD, tmp, 4);
$display("%2d: 0x4%x",i, (tmp & `PSU_PTD_TX_RAM_RD_DAT) >> `PSU_PTD_TX_RAM_RD_DAT_OFFSET);
end
m_acc.write(m_base + `ADDR_PSU_PTD, 'h0000);
endtask;
endclass // CSimDrv_PSU
`endif // `ifndef __SIMDRV_PSU_SVH
testbench/scb_top/main.sv
View file @ eef777b5
......@@ -6,6 +6,7 @@
`include "simdrv_wr_tru.svh"
`include "simdrv_txtsu.svh"
`include "simdrv_tatsu.svh"
`include "simdrv_psu.svh"
`include "simdrv_hwdu.svh"
`include "endpoint_regs.v"
`include "endpoint_mdio.v"
......@@ -81,6 +82,7 @@ module main;
CSimDrv_WR_TRU tru;
CSimDrv_TXTSU txtsu;
CSimDrv_TATSU tatsu;
CSimDrv_PSU psu;
CSimDrv_HWDU hwdu;
EthPacket ptpAnnounce;
......@@ -356,6 +358,14 @@ module main;
integer g_send_announce_from_NIC = 0;
reg [g_max_ports-1:0] announceTxVector = 18'b111111111111111111;
reg [31:0] psu_tx_mask = 18'b000000000000001111;
reg [31:0] psu_rx_mask = 18'b000000000000001000;
reg [15:0] psu_hldvr_clk_class= 7;
reg [ 2:0] psu_inj_prio = 0;
bit ignore_rx_port_id = 0;
bit psu_enable = 0;
integer g_psu_test = 0;
/** *************************** test scenario 1 ************************************* **/
/*
* testing switch over between ports 0,1,2
......@@ -2952,7 +2962,7 @@ module main;
ptpAnnounce.payload[i] = ANNOUNCE_templ[i];
g_send_announce_from_NIC = 10; // ten times to all ports
g_psu_test =1;
end
//*/
//////////////////////////////////////////////////////////////////////////////////////////////
......@@ -3848,7 +3858,11 @@ module main;
txtsu = new (cpu_acc, 'h51000);
txtsu.init();
$display("InitPSU");
psu = new (cpu_acc, 'h70000);
psu.init(psu_inj_prio,psu_hldvr_clk_class,ignore_rx_port_id, psu_rx_mask, psu_tx_mask);
$display("Initialization done");
rtu = new;
......@@ -4695,9 +4709,25 @@ module main;
end
join_none; //
fork // testing PSU
begin
if(g_psu_test > 0)
begin
wait_cycles(100);
psu.enable(1);
wait_cycles(1300);
psu.dbg_holdover(1);
wait_cycles(1300);
psu.dbg_holdover(0);
wait_cycles(1300);
psu.dbg_dump_tx_ram();
end
end
join_none; //
end
/* ***************************************************************************************
/* **************************************************************************************
* Page allocator and resource manager debugging
* ***************************************************************************************
* this stuff is used to debug allocator and resource manager - it is very slow and has
......
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