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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit ece8fde7 authored by Marek Gumiński's avatar Marek Gumiński
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Updated wr-cores-local with version merged with 

99dc19ae4b9ab761d8c0a4bbce9280b41afe19d4
parent 3f10e63b
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Showing with 1145 additions and 971 deletions
wr-cores @ 19117f27
Subproject commit 031525ad956f93ae6f14090cf3eadcc592f82ef9
Subproject commit 19117f273963055a1d05353a5cd1e68882624eec
ip_cores/wr-cores-local/modules/wr_endpoint/ep_autonegotiation.vhd
View file @ ece8fde7
......@@ -158,7 +158,7 @@ begin -- syn
-- make the code more readable
ability_match <= an_rx_valid_i;
acknowledge_match <= an_rx_valid_i and an_rx_val_i(14);
consistency_match <= '1' when (an_rx_valid_i = '1' and rx_config_reg (15) = an_rx_val_i(15) and rx_config_reg(13 downto 0) = an_rx_val_i(13 downto 0)) else '0';
consistency_match <= '1' when (an_rx_valid_i = '1' and rx_config_reg (15) = an_rx_val_i(15) and rx_config_reg(13 downto 0) = an_rx_val_i(13 downto 0));
-- process: main auto-negotiation state machine. More or less compatible with
......
ip_cores/wr-cores-local/modules/wr_nic/nic_descriptor_manager.vhd
View file @ ece8fde7
......@@ -137,7 +137,7 @@ begin -- behavioral
-- variable l:line ;
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0' or enable_i = '0') then
if(rst_n_i = '0') then
desc_write_done_o <= '0';
desc_grant_o <= '0';
state <= ARB_START_SCAN;
......
ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_wb_slave.wb
View file @ ece8fde7
......@@ -406,6 +406,53 @@ peripheral {
prefix = "TAG";
trigger = LEVEL_1;
};
reg {
name = "Port state register (direct access)";
prefix = "PSR";
field {
name = "States";
prefix = "STATES";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "PTP support unit (direct notification)";
prefix = "PSU";
field {
name = "Holdover State";
prefix = "HOLDOVER";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Received Announce with Holdover clock Class, write 1 to clear";
description = "Informs about detection of Announce message that indactes the upstream clocks are in holdover:\
Read 0: no mesasage detected \
Read 1: detected announce with configured clockClass at configured active slave \
Write 1: clear flag.";
prefix = "RX_HOLDOVER_MSG";
load = LOAD_EXT;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "Mask which indicates which reference input is used (i.e. active slave port)";
prefix = "SELECTED_REF_ID";
size = 5;
align = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
ip_cores/wr-cores-local/modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ ece8fde7
......@@ -152,6 +152,18 @@ entity wr_softpll_ng is
irq_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
-- rx clock states (port up/down)
clk_rx_status_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) :=(others=>'0');
-- mask which indicates which reference is currently used (i.e. active port)
-- should be only one at at time
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
-- 1: SoftPLL is in holdover mode
-- 0: not in holdover (either locked or free-running)
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
rx_holdover_clr_o : out std_logic;
-- Debug FIFO readout interrupt
dbg_fifo_irq_o : out std_logic
);
......@@ -325,6 +337,8 @@ architecture rtl of wr_softpll_ng is
signal aligner_sample_valid, aligner_sample_ack : std_logic_vector(g_num_outputs downto 0);
signal aligner_sample_cref, aligner_sample_cin : t_aligner_sample_array;
signal psu_selected_ref_mask : std_logic_vector(31 downto 0);
-- necessary to be able to relax timing from spll_aligner outputs cref and
-- cin (driven by ref clock) to the registers (driven by sys clock). The two
-- sides are already sychronized via a gc_pulse_synchronizer, which makes
......@@ -795,6 +809,9 @@ begin -- rtl
regs_out.csr_n_ref_i <= std_logic_vector(to_unsigned(g_num_ref_inputs, regs_out.csr_n_ref_i'length));
regs_out.csr_n_out_i <= std_logic_vector(to_unsigned(g_num_outputs, regs_out.csr_n_out_i'length));
regs_out.psr_states_i(g_num_ref_inputs-1 downto 0 )<= clk_rx_status_i;
regs_out.psr_states_i(regs_out.psr_states_i'length-1 downto g_num_ref_inputs)<= (others =>'0');
dac_dmtd_load_o <= regs_in.dac_hpll_wr_o;
dac_dmtd_data_o <= regs_in.dac_hpll_o;
......@@ -809,4 +826,11 @@ begin -- rtl
regs_out.f_ext_valid_i <= '0';
regs_out.trr_disc_i <= '0';
holdover_on_o <= regs_in.psu_holdover_o;
psu_selected_ref_mask <= f_onehot_encode(regs_in.psu_selected_ref_id_o);
selected_ref_clk_o <= psu_selected_ref_mask(g_num_ref_inputs-1 downto 0);
regs_out.psu_rx_holdover_msg_i <= rx_holdover_msg_i;
rx_holdover_clr_o <= '1' when (regs_in.psu_rx_holdover_msg_o = '1' and regs_in.psu_rx_holdover_msg_load_o ='1') else '0';
end rtl;
ip_cores/wr-cores-local/modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ ece8fde7
......@@ -127,6 +127,12 @@ entity xwr_softpll_ng is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- rx clock states (port up/down)
clk_rx_status_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) :=(others=>'0');
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
rx_holdover_clr_o : out std_logic;
int_o: out std_logic;
......@@ -185,6 +191,11 @@ architecture wrapper of xwr_softpll_ng is
wb_stall_o : out std_logic;
irq_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
clk_rx_status_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) :=(others=>'0');
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
rx_holdover_clr_o : out std_logic;
dbg_fifo_irq_o : out std_logic);
end component;
......@@ -238,6 +249,11 @@ begin -- behavioral
wb_stall_o => slave_o.stall,
irq_o => int_o,
debug_o => debug_o,
clk_rx_status_i => clk_rx_status_i,
selected_ref_clk_o => selected_ref_clk_o,
holdover_on_o => holdover_on_o,
rx_holdover_msg_i => rx_holdover_msg_i,
rx_holdover_clr_o => rx_holdover_clr_o,
dbg_fifo_irq_o => dbg_fifo_irq_o);
slave_o.err <= '0';
......
ip_cores/wr-cores-local/sim/eth_packet.svh
View file @ ece8fde7
......@@ -32,6 +32,7 @@ class EthPacket;
byte payload[];
int size;
int tx_wr_port;
mac_addr_t src, dst;
oob_type_t oob_type;
......@@ -64,6 +65,7 @@ class EthPacket;
is_hp = 0;
has_crc = 0;
oob_type = NONE;
tx_wr_port=-1;
payload = new[size](payload);
endfunction // new
......@@ -246,6 +248,9 @@ is_hp ? "H" : " ", has_crc ? "C" : " ");
hexdump(payload);
endtask // dump
task set_tx_wr_port(int port);
tx_wr_port = port;
endtask
endclass // EthPacket
......
ip_cores/wr-cores-local/sim/simdrv_wr_nic.svh
View file @ ece8fde7
......@@ -275,10 +275,7 @@ class CSimDrv_NIC;
desc.length = payload.size();
desc.pad_e = (desc.length < 60 ? 1 : 0);
desc.ts_e = (pkt.oob == TX_FID ? 1: 0);
if(pkt.tx_wr_port >=0)
desc.dpm = 32'hffffffff & (1<<pkt.tx_wr_port);
else
desc.dpm = 32'hffffffff;
desc.dpm = 32'hffffffff;
desc.ts_id = tx_oob_fid++;
desc.ready = 1;
desc.error = 0;
......
ip_cores/wr-cores-local/sim/softpll_regs_ng.vh
View file @ ece8fde7
......@@ -59,6 +59,16 @@
`define SPLL_DFR_SPLL_VALUE 32'h7fffffff
`define SPLL_DFR_SPLL_EOS_OFFSET 31
`define SPLL_DFR_SPLL_EOS 32'h80000000
`define ADDR_SPLL_PSR 8'h50
`define SPLL_PSR_STATES_OFFSET 0
`define SPLL_PSR_STATES 32'hffffffff
`define ADDR_SPLL_PSU 8'h54
`define SPLL_PSU_HOLDOVER_OFFSET 0
`define SPLL_PSU_HOLDOVER 32'h00000001
`define SPLL_PSU_RX_HOLDOVER_MSG_OFFSET 1
`define SPLL_PSU_RX_HOLDOVER_MSG 32'h00000002
`define SPLL_PSU_SELECTED_REF_ID_OFFSET 8
`define SPLL_PSU_SELECTED_REF_ID 32'h00001f00
`define ADDR_SPLL_EIC_IDR 8'h60
`define SPLL_EIC_IDR_TAG_OFFSET 0
`define SPLL_EIC_IDR_TAG 32'h00000001
......
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