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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit e21fe545 authored by Marek Gumiński's avatar Marek Gumiński
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Changed data width in wr_nic

parent ecc68af2
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Showing with 38 additions and 31 deletions
ip_cores/wr-cores-local/modules/fabric/wr_fabric_pkg.vhd
View file @ e21fe545
......@@ -182,7 +182,7 @@ package wr_fabric_pkg is
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
data_o : out std_logic_vector(63 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
......
ip_cores/wr-cores-local/modules/fabric/xwb_fabric_sink.vhd
View file @ e21fe545
......@@ -56,7 +56,7 @@ entity xwb_fabric_sink is
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
data_o : out std_logic_vector(63 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
......@@ -69,7 +69,8 @@ end xwb_fabric_sink;
architecture rtl of xwb_fabric_sink is
constant c_fifo_width : integer := 16 + 2 + 4;
constant c_data_width : integer := 64;
constant c_fifo_width : integer := c_data_width + 2 + 4;
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
......@@ -78,7 +79,7 @@ architecture rtl of xwb_fabric_sink is
signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(1 downto 0);
signal post_data : std_logic_vector(15 downto 0);
signal post_data : std_logic_vector(63 downto 0);
signal snk_out : t_wrf_sink_out;
......@@ -107,9 +108,9 @@ begin -- rtl
pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(15 downto 0) <= snk_i.dat;
fin(17 downto 16) <= snk_i.adr;
fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
fin(c_data_width-1 downto 0) <= snk_i.dat;
fin(c_data_width+2-1 downto c_data_width) <= snk_i.adr;
fin(c_data_width+2+4-1 downto c_data_width+2) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
......@@ -129,7 +130,7 @@ begin -- rtl
snk_o <= snk_out;
we <= '1' when fin(21 downto 18) /= "0000" and full = '0' else '0';
we <= '1' when fin(c_data_width+2+4-1 downto c_data_width+2) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
......@@ -158,17 +159,17 @@ begin -- rtl
end process;
post_data <= fout_reg(15 downto 0);
post_addr <= fout_reg(17 downto 16);
post_sof <= fout_reg(21) and rd_d0; --and q_valid;
post_data <= fout_reg(c_data_width-1 downto 0);
post_addr <= fout_reg(c_data_width+2-1 downto c_data_width);
post_sof <= fout_reg(c_data_width+2+3) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(18);
post_dvalid <= fout_reg(c_data_width+2+0);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = c_WRF_STATUS) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
eof_o <= fout_reg(20) and rd_d0;
bytesel_o <= fout_reg(19);
eof_o <= fout_reg(c_data_width+2+2) and rd_d0;
bytesel_o <= fout_reg(c_data_width+2+1);
data_o <= post_data;
addr_o <= post_addr;
......@@ -221,7 +222,7 @@ architecture wrapper of wb_fabric_sink is
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
data_o : out std_logic_vector(63 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
......
ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_pkg.vhd
View file @ e21fe545
......@@ -68,7 +68,7 @@ package endpoint_pkg is
bytesel : std_logic;
has_rx_timestamp : std_logic;
rx_timestamp_valid : std_logic;
data : std_logic_vector(15 downto 0);
data : std_logic_vector(63 downto 0);
addr : std_logic_vector(1 downto 0);
end record;
type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
......
ip_cores/wr-cores-local/modules/wr_nic/nic_elastic_buffer.vhd
View file @ e21fe545
......@@ -73,7 +73,8 @@ architecture rtl of nic_elastic_buffer is
end function log2;
constant c_fifo_width : integer := 16 + 2 + 5;
constant c_data_width : integer := 64;
constant c_fifo_width : integer := c_data_width + 2 + 5;
signal fifo_write : std_logic;
signal fifo_read : std_logic;
......@@ -183,12 +184,12 @@ begin -- rtl
almost_full_o => fifo_almost_full
);
fab_o.data <= fifo_out_ser(15 downto 0);
fab_o.addr <= fifo_out_ser(17 downto 16);
fab_o.error <= fifo_out_ser(18) and output_valid;
fab_o.dvalid <= fifo_out_ser(19) and output_valid;
fab_o.eof <= fifo_out_ser(20) and output_valid;
fab_o.sof <= fifo_out_ser(21) and output_valid;
fab_o.bytesel <= fifo_out_ser(22);
fab_o.data <= fifo_out_ser(c_data_width-1 downto 0);
fab_o.addr <= fifo_out_ser(c_data_width+2-1 downto c_data_width);
fab_o.error <= fifo_out_ser(c_data_width+2) and output_valid;
fab_o.dvalid <= fifo_out_ser(c_data_width+3) and output_valid;
fab_o.eof <= fifo_out_ser(c_data_width+4) and output_valid;
fab_o.sof <= fifo_out_ser(c_data_width+5) and output_valid;
fab_o.bytesel <= fifo_out_ser(c_data_width+6);
end rtl;
ip_cores/wr-cores-local/modules/wr_nic/nic_rx_fsm.vhd
View file @ e21fe545
......@@ -439,7 +439,7 @@ begin
end if;
if(oob_sreg (2) = '1') then -- 3rd OOB word
cur_rx_desc.ts_r(15 downto 0) <= fab_in.data;
cur_rx_desc.ts_r(15 downto 0) <= fab_in.data(15 downto 0);
cur_rx_desc.got_ts <= '1';
end if;
end if;
......
ip_cores/wr-cores-local/modules/wr_nic/nic_tx_fsm.vhd
View file @ e21fe545
......@@ -325,7 +325,8 @@ begin -- behavioral
ackcnt_nrst <= '1';
src_o.adr <= c_WRF_STATUS;
src_o.sel <= "11";
src_o.dat <= f_marshall_wrf_status(default_status_reg);
src_o.dat <= (others=>'0');
src_o.dat(15 downto 0) <= f_marshall_wrf_status(default_status_reg);
if( src_i.stall = '0' and buf_grant_i = '0') then
src_stb_int <= '1';
......@@ -345,7 +346,8 @@ begin -- behavioral
cur_tx_desc.error <= '1';
elsif( src_i.stall = '0' ) then
src_o.adr <= c_WRF_DATA;
src_o.dat <= tx_data_reg(31 downto 16);
src_o.dat <= (others=>'0');
src_o.dat(15 downto 0) <= tx_data_reg(31 downto 16);
ignore_first_hword <= '0';
src_stb_int <= not ignore_first_hword;
......@@ -378,7 +380,8 @@ begin -- behavioral
cur_tx_desc.error <= '1';
elsif( src_i.stall='0' and buf_grant_i = '0') then
src_o.adr <= c_WRF_DATA;
src_o.dat <= tx_data_reg(15 downto 0);
src_o.dat <= (others=>'0');
src_o.dat(15 downto 0) <= tx_data_reg(15 downto 0);
src_stb_int <= '1';
if(tx_cntr_expired = '0') then
......@@ -416,7 +419,7 @@ begin -- behavioral
state <= TX_UPDATE_DESCRIPTOR;
cur_tx_desc.error <= '1';
elsif( src_i.stall='0' ) then
src_o.dat <= x"0000";
src_o.dat <= (others=>'0');
src_o.adr <= c_WRF_DATA;
src_o.sel <= "11";
src_stb_int <= '1';
......@@ -438,7 +441,8 @@ begin -- behavioral
src_o.sel <= "11";
if( src_i.stall='0' ) then
src_o.dat <= c_WRF_OOB_TYPE_TX & x"000";
src_o.dat <= (others=>'0');
src_o.dat(15 downto 0) <= c_WRF_OOB_TYPE_TX & x"000";
src_o.adr <= c_WRF_OOB;
src_stb_int <= '1';
state <= TX_OOB2;
......@@ -448,7 +452,8 @@ begin -- behavioral
src_o.sel <= "11";
if( src_i.stall='0' ) then
src_o.dat <= cur_tx_desc.ts_id;
src_o.dat <= (others=>'0');
src_o.dat(15 downto 0) <= cur_tx_desc.ts_id;
src_o.adr <= c_WRF_OOB;
src_stb_int <= '1';
state <= TX_END_PACKET;
......
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