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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit a05d2f21 authored by Marek Gumiński's avatar Marek Gumiński
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Automatic reformatting of xdc done by vivado. 

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parent 16c02da4
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Showing with 8 additions and 8 deletions
top/scb_18ports/scb_top_synthesis.xdc
View file @ a05d2f21
create_clock -period 40.000 -name clk_boot -waveform {0.000 20.000} [get_ports fpga_clk_25mhz_p_i]
create_clock -period 16.000 -name clk_dmtd -waveform {0.000 8.000} [get_ports fpga_clk_dmtd_p_i]
create_clock -period 16.000 -name clk_ref -waveform {0.000 8.000} [get_ports fpga_clk_ref_p_i]
create_clock -period 16.000 -name clk_ref -waveform {0.000 8.000} [get_ports fpga_clk_ref_p_i]
create_clock -period 8.000 -name clk_gtx_0 -waveform {0.000 4.000} [get_ports gtx_clk_p_i[0]]
create_clock -period 8.000 -name clk_gtx_1 -waveform {0.000 4.000} [get_ports gtx_clk_p_i[1]]
create_clock -period 8.000 -name clk_gtx_2 -waveform {0.000 4.000} [get_ports gtx_clk_p_i[2]]
create_clock -period 8.000 -name clk_gtx_3 -waveform {0.000 4.000} [get_ports gtx_clk_p_i[3]]
create_clock -period 8.000 -name clk_gtx_4 -waveform {0.000 4.000} [get_ports gtx_clk_p_i[4]]
create_clock -period 8.000 -name clk_gtx_0 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[0]}]
create_clock -period 8.000 -name clk_gtx_1 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[1]}]
create_clock -period 8.000 -name clk_gtx_2 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[2]}]
create_clock -period 8.000 -name clk_gtx_3 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[3]}]
create_clock -period 8.000 -name clk_gtx_4 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[4]}]
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/Ophy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/Ophy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/Ophy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
......@@ -133,7 +133,7 @@ set_clock_groups -asynchronous -group clk_500
set_clock_groups -asynchronous -group clk_fb_1
set_clock_groups -asynchronous -group clk_500_1
set_property PACKAGE_PIN D10 [get_ports {cpu_addr_i[0]}]
set_property PACKAGE_PIN F12 [get_ports {cpu_addr_i[1]}]
set_property PACKAGE_PIN E12 [get_ports {cpu_addr_i[2]}]
......
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