Merge branch '10gb'

8072e017 · Marek Gumiński · e56347f9 · c64abe14 · 8072e017 · 8072e017
Commit 8072e017 authored Sep 12, 2019 by Marek Gumiński
855 changed files
--- a/.gitignore
+++ b/.gitignore
+*.*\#
+\#*
+.\#*
+*.*~
+work
+*.wlf
+modelsim.ini
+transcript
+*.vstf
+fifo_generator_v6_1
+*.zip
+*.xdl
+build_wb.sh
+synthesis_descriptor.vhd
--- a/.gitmodules
+++ b/.gitmodules
+[submodule "ip_cores/general-cores"]
+	path = ip_cores/general-cores
+	url = ../general-cores.git
+[submodule "ip_cores/wr-cores"]
+	path = ip_cores/wr-cores
+	url = ../wr-cores.git
--- a/Manifest.py
+++ b/Manifest.py
+modules = { "local" : [
+				"modules/wrsw_rt_subsystem",
+				"modules/wrsw_swcore",
+				"modules/wrsw_rtu",
+				"modules/wrsw_tru",
+				"modules/wrsw_tatsu",
+				"modules/wrsw_pstats",
+				"modules/wrsw_psu",
+        "modules/wrsw_hwiu",
+        "modules/wrsw_watchdog",
+				"platform/virtex6/chipscope",
+				"platform/xilinx",
+				"ip_cores/wr-cores-local",
+				"ip_cores/general-cores"],
+};
--- a/README
+++ b/README
--- a/doc/notes.txt
+++ b/doc/notes.txt
+Functional changes/problems:
+- Output delay has different resolution (not sure about max value)
+- Minimal frequency of MMCM reference clock is ~14 MHz. Can't be used in ext_pll
+
+
+Alarmin warnings:
+
+	[Timing 38-316] Clock period '16.000' specified during out-of-context synthesis of instance 'phy_block.phys' at clock pin 'rxusrclk2_in[0]' is different from the actual clock period '4.000', this can lead to different synthesis results.
+
+	[Synth 8-3352] multi-driven net \rsp_o[18][port_mask] [0] with 1st driver pin 'U_Real_Top/gen_network_stuff.U_Nic/U_TX_FSM/cur_tx_desc_reg[dpm][18]/Q' ["/home/gumas/projects/cti/wr/wrs_evaluation/wr-switch-hdl/ip_cores/wr-cores-local/modules/wr_nic/nic_tx_fsm.vhd":186]
+
+	[Synth 8-3352] multi-driven net O915[17] with 1st driver pin 'i_102136/O' ["/home/gumas/projects/cti/wr/wrs_evaluation/wr-switch-hdl/modules/wrsw_psu/psu_announce_snooper.vhd":188]
--- a/doc/report/.gitignore
+++ b/doc/report/.gitignore
+*.aux
+*.log
+*.out
+*.toc
+*.xwm
\ No newline at end of file
--- a/doc/report/cti_style_doc.tex
+++ b/doc/report/cti_style_doc.tex
+\addtolength{\textwidth}{3cm}
+\addtolength{\hoffset}{-1.5cm}
+\addtolength{\textheight}{3cm}
+\addtolength{\voffset}{-1.5cm}
+\usepackage[utf8]{inputenc}
+\usepackage[english]{babel}
+\usepackage[T1]{fontenc}
+\usepackage{textcomp}
+\usepackage{amsmath}
+\usepackage[textwidth=40]{todonotes}
+%\usepackage{todonotes}
+%\usepackage[disable]{todonotes}
+%\usepackage{titlesec}
+\usepackage{amsfonts}
+\usepackage{amssymb}
+\usepackage{gensymb}
+\usepackage{longtable}
+\usepackage{makeidx}
+\usepackage{indentfirst}
+\usepackage{graphicx}
+%\usepackage{tabularx}
+\usepackage{epstopdf}
+\usepackage{lmodern}
+\usepackage{color}
+\usepackage{xcolor}
+\usepackage{url}
+\usepackage{subfiles}
+\usepackage{hhline}
+\usepackage{nameref}
+\usepackage{float}
+\usepackage{wrapfig}
+\usepackage{lastpage}
+\makeatletter
+\newcommand*{\currentname}{\@currentlabelname}
+\makeatother
+\usepackage[printwatermark]{xwatermark}
+\usepackage{pdfpages}
+\usepackage{multirow}
+\usepackage{svg}
+\setsvg{inkscape = inkscape -z -D}
+\usepackage[toc,page]{appendix}
+\usepackage{caption}
+\usepackage{listings}
+\usepackage[graphicx]{realboxes}
+\usepackage{array}
+\usepackage{placeins}
+\graphicspath{{./},{./img/}}
+\newcommand{\figref}{Fig.~\ref}
+%\renewcommand{\bibname}{References}
+\definecolor{gray}{rgb}{0.4,0.4,0.4}
+\definecolor{lgray}{rgb}{0.8,0.8,0.8}
+\definecolor{lred}{rgb}{1,0.4,0.4}
+\definecolor{darkblue}{rgb}{0.0,0.0,0.6}
+\definecolor{cyan}{rgb}{0.0,0.6,0.6}
+%\newwatermark*[allpages,color=lred,angle=-45,scale=1,xpos=105,ypos=118]{DRAFT}
+\newwatermark*[allpages,scale=0.4,xpos=-57,ypos=120]{\includegraphics{template_img/logo_cti.png}}
+%\usepackage[left=2cm,right=2cm,top=2cm,bottom=2cm]{geometry}
+\usepackage{fancyhdr}
+\pagestyle{fancy}
+\lhead{}
+\rhead{\CtiHeader}
+
+\usepackage{lastpage}
+\newcommand*{\thesecondlastpage}{%
+  \the\numexpr(\getrefbykeydefault{LastPage}{page}{0})\relax
+}
+\AtBeginDocument{\refused{LastPage}}
+
+\rfoot{Page \thepage \hspace{1pt} of \thesecondlastpage}
+\usepackage{hyperref}
+\hypersetup{
+colorlinks,
+citecolor=black,
+filecolor=black,
+linkcolor=blue,
+urlcolor=blue
+}
+
+% Make fonts sans serif
+\usepackage[T1]{fontenc}
+\usepackage[sfdefault]{AlegreyaSans}
+\renewcommand*\oldstylenums[1]{{\AlegreyaSansOsF #1}}
+%\usepackage{DejaVuSansCondensed}
+%\renewcommand*\familydefault{\sfdefault}
+%\usepackage[T1]{fontenc}
+
+%\usepackage[scaled]{helvet}
+%\renewcommand\familydefault{\sfdefault}
+%\usepackage[T1]{fontenc}
+
+
+\sloppy
+
+%\renewcommand{\bibname}{References}
+%------------------------------------------------------
+
+%------------------------------------------------------
+%zaczynaj każdą sekcję na nowej stronie
+%\let\oldsection\section
+%\renewcommand\section{\clearpage\oldsection}
+
+\renewcommand{\footrulewidth}{1pt}
+%% if footer
+\lfoot{
+Creotech Instruments S.A. \hspace{15pt} tel. +48 22 233 10 27    \\
+ul. Gen. L. Okulickiego 7/9    \hspace{9pt} e-mail: support@creotech.pl \\
+05-500 Piaseczno, Poland    \hspace{23pt}    www.creotech.pl
+}
+%% endif
+\cfoot{}
+
+% Some vertical spacing definitions
+\newcommand{\afterTitleVerticalSpacing}{0.3cm}
+\newcommand{\fieldVerticalSpacing}{0.3cm}
+\newcommand{\afterActionVerticalSpacing}{0.3cm}
+
+% Prevent visible subsection numbers
+\setcounter{secnumdepth}{1}
+
+\renewcommand*\contentsname{Table of Contents}
--- a/doc/report/images/fpga_over.png
+++ b/doc/report/images/fpga_over.png
--- a/doc/report/images/fpga_over_edit.pdf
+++ b/doc/report/images/fpga_over_edit.pdf
--- a/doc/report/images/phy_10g.png
+++ b/doc/report/images/phy_10g.png
--- a/doc/report/images/phy_1g.png
+++ b/doc/report/images/phy_1g.png
--- a/doc/report/images/wrs.png
+++ b/doc/report/images/wrs.png
--- a/doc/report/main.pdf
+++ b/doc/report/main.pdf
--- a/doc/report/main.tex
+++ b/doc/report/main.tex
+\documentclass[12pt,a4paper,final,titlepage]{article}
+
+\input{"cti_style_doc.tex"}
+
+\newcommand{\CtiDocumentTitle}{WRS resource utilisation }
+\newcommand{\CtiHeader}{Evaluation of WRS firmware resource utilisation}
+\newcommand{\CtiSubtitle}{on Xilinx US+ FPGA}
+\newcommand{\CtiDocumentLogo}{images/wrs.png}
+
+\hypersetup{pdfinfo={
+Title=\CtiDocumentTitle,
+Author={Creotech Instruments S.A.}}
+}
+
+\usepackage{enumitem}
+
+\begin{document}
+
+    \input{ "title_page.tex" }
+
+    
+    % Remove indentation after title page
+	\setlength{\parindent}{0pt}
+
+	\tableofcontents
+	\clearpage
+
+	\section{Introduction}
+
+		Presented report summarizes evaluation of White Rabbit Switch (WRS) firmware resource evaluation. Firmware is evaluated for Xilinx Zynq UltraScale+ (US+) MPSoC XCZU11EG-1FFVC1156E \ref{fig:fpga_over}.
+
+		\begin{figure}[h]
+			
+			\caption{US+ FPGA family resource overview (\href{https://www.xilinx.com/support/documentation/data_sheets/ds891-zynq-ultrascale-plus-overview.pdf}{DS891}).}
+			\label{fig:fpga_over}
+			\includegraphics[scale=.65]{images/fpga_over_edit.pdf}
+		\end{figure}
+
+		The firmware was supposed to be tested in following configurations:
+		\begin{enumerate}
+			\item 1G Ethernet - based on current proposed\_master branch
+			\item 1G Ethernet with redundancy support (see \ref{ssec:redundancy})
+			\item 10G Ethernet
+			\item 10G Ethernet with redundancy support (see \ref{ssec:redundancy})
+		\end{enumerate}
+
+		The firmware didn't have to be functional nor did it need to implement.
+
+	\section{Work done}
+
+		\subsection{Build system}
+			Project used to evaluate resource utilisation may be easily rebuild with HDLmake. It required small changes in syn/scb\_18ports/Manifest.py file.
+
+		\subsection{Block RAM}
+			Netlist representation of Block RAM was replaced by Xilinx Parametized Macro (XPM).
+			
+			Netlists were removed because they are are not supported by Vivado.
+
+		\subsection{Xilinx primitives}
+			Input and output buffer primitives have been replaced by US+ family counterparts.
+
+			Some changes were also required in block platform/xilinx/oserdes\_8\_to\_1.vhd. Oserdes resolution has increased in US+.
+
+		\subsection{Gigabit transceivers}
+			Original Ethernet phys have been replaced with Xilinx IPcore "UltraScale FPGAs Transceivers Wizard". Separate versions were created for 1G Ethernet (line rate 1.25 Gb/s, 125 MHz clock, 20b internal data width \ref{fig:1g_conf}) and 10G Ethernet (line rate 12.5, 156.25 MHz clock, 40b internal data width \ref{fig:10g_conf}).
+
+			A generate loop (concatenate\_gen) was added to scb\_top\_synthesis to adjust existing phy interface to IPcore ports. Interconnect between the design and phys is unlikely to be functional, but should prevent Vivado from removing any major components.
+
+			\begin{figure}[h]
+				\caption{Gigabit transceivers configuration}
+				\label{fig:1g_conf}
+				\includegraphics[scale=0.5]{images/phy_1g.png}
+			\end{figure}
+
+			\begin{figure}[h]
+				\caption{10 Gigabit transceivers configuration}
+				\label{fig:10g_conf}
+				\includegraphics[scale=0.5]{images/phy_10g.png}
+			\end{figure}
+
+		\subsection{Redundancy support}
+			\label{ssec:redundancy}
+			Code required to implement link redundancy was developed by Maciej Lipiński. It is available in ohwr repository in branches ML-PTP-support-150317 and TRUandRTUandEndpointAndSWcoreAndTATSU.
+
+			Branch TRUandRTUandEndpointAndSWcoreAndTATSU was already merged with proposed master. Following generics had to be activated in scb\_top\_bare instantiation in order to evaluate resource utilisation of TRU and TATSU components: g\_with\_TRU, g\_with\_TATSU.
+
+			Branch ML-PTP-support-150317 required merging into proposed\_master. Regular merging proved to be difficult, due to multiple merge conflicts. Instead ML-PTP-support-150317 was rebased on proposed master. This way conflicts in consecutive commits could be resolved one by one.
+			A PSU (component that is added in this branch) may be enabled with generic g\_with\_PSU.
+
+
+		\subsection{10Gb link}
+
+			Migration to 10Gb link requires changing reference clock frequency and link data width. Frequency change doesn't effect resource utilisation. Timing is not even verified during synthesis.
+
+			
+			Change of the data width requires changes in some parts of the design. 
+
+			Most of components passes the data as is, so it is sufficient to change record declaration in vhdl packages.
+			Vectors t\_wrf\_source\_out.dat, t\_phyif\_output.tx\_data and t\_phyif\_input.rx\_data were resized from 16 to 64 bytes.
+
+			The endpoint on the other hand contains multiple comparisons and assignments that assume certain (16 bit) data width. Changing data width in this component would require rewriting multiple FSM's.
+
+			It was decided to instantiate 4 endpoints in parallel instead. Each of the multiplicated endpoints processes 16 bit of the 64 data word received from the phys. Other control signals (rx\_k, tx\_disparity etc) are connected to all 4 endpoints. Data output of the endpoints is concatenated back into 64 bit array. Other outputs of the endpoints are xored in order to make sure that nothing will be over optimised during synthesis. Vector t\_ep\_internal\_fabric.data has original 16 bit width.
+
+			The interface between original existing signals and multiplicated endpoint is located inside U\_Real\_Top/gen\_endpoints\_and\_phys generate loop.
+
+	\section{Found issues}
+
+		\subsection{Ext PLL} % (fold)
+			A minimal frequency of MMCM block was increased to ~14Mhz in US+ family. A U\_Ext\_PLL1 that generated 100 MHz clock from 10 MHz input will will not work correctly in US+ FPGA.
+		
+		\subsection{Latch} % (fold)
+			A latch reported by Vivado was fixed in commit 16c02da485ed4aaea17b8c242b52b40d2cc2481c.
+
+
+	\section{Summary}
+
+		Figures \ref{fig:1g_nored_res}, \ref{fig:1g_red_res}, \ref{fig:10g_nored_res} and \ref{fig:10g_red_res} show resource utilisation estimated by Vivado IDE.
+
+		Resource utilisation with 10 Gb links barely reaches 50\% on LUT's and 45\% on BRAM.
+
+		\begin{figure}[h]
+			\caption{Resource utilisation with 1Gb serial links and without redundancy components.}
+			\label{fig:1g_nored_res}
+			\includegraphics[scale=0.75]{../resource_util_screenshots/1g_noredundancy.png}
+		\end{figure}
+		
+		\begin{figure}[h]
+			\caption{Resource utilisation with 1Gb serial links and with redundancy components enabled.}
+			\label{fig:1g_red_res}
+			\includegraphics[scale=0.75]{../resource_util_screenshots/1g_redundancy_2.png}
+		\end{figure}
+
+		\begin{figure}[h]
+			\caption{Resource utilisation with 10Gb serial links and without redundancy components.}
+			\label{fig:10g_nored_res}
+			\includegraphics[scale=0.75]{../resource_util_screenshots/10g_noredundancy.png}
+		\end{figure}
+		
+		\begin{figure}[h]
+			\caption{Resource utilisation with 10Gb serial links and with redundancy components enabled.}
+			\label{fig:10g_red_res}
+			\includegraphics[scale=0.75]{../resource_util_screenshots/10g_redundancy_2.png}
+		\end{figure}
+
+\end{document}
--- a/doc/report/template_img/kropki-eps-converted-to.pdf
+++ b/doc/report/template_img/kropki-eps-converted-to.pdf
--- a/doc/report/template_img/kropki.eps
+++ b/doc/report/template_img/kropki.eps
--- a/doc/report/template_img/logo_cti.png
+++ b/doc/report/template_img/logo_cti.png
--- a/doc/report/title_page.tex
+++ b/doc/report/title_page.tex
+\begin{titlepage}
+
+	\textcolor{white}{xxx}
+
+	\vskip 1 true in
+
+	% \begin{center}
+	% 	\textbf{{\Huge \CtiDocumentTitle}} \bigskip
+	% \end{center}
+
+	\begin{wrapfigure}{l}{0.01\textwidth}
+		\begin{center}
+			\vspace{-35pt}
+			\includegraphics[scale=0.5]{template_img/kropki.eps}
+		\end{center}
+	\end{wrapfigure}
+	
+	
+
+
+	\textbf{{\Huge \CtiDocumentTitle}} \\
+
+	\textbf{ {\indent \indent \LARGE \mbox{\CtiSubtitle}}}\\
+
+	\vskip 0.8 true in
+
+	\begin{figure}[htbp!]
+		\centering
+		\includegraphics[width=14.5cm,height=15cm,keepaspectratio]{\CtiDocumentLogo}\\
+	\end{figure}
+
+	\begin{center}
+	\end{center}
+
+	\vskip 0.7 true in
+
+\end{titlepage}
+
+
+
+
--- a/doc/resource_util_screenshots/10g_noredundancy.png
+++ b/doc/resource_util_screenshots/10g_noredundancy.png
--- a/doc/resource_util_screenshots/10g_redundancy.png
+++ b/doc/resource_util_screenshots/10g_redundancy.png
--- a/doc/resource_util_screenshots/1g_noredundancy.png
+++ b/doc/resource_util_screenshots/1g_noredundancy.png
--- a/doc/resource_util_screenshots/1g_redundancy.png
+++ b/doc/resource_util_screenshots/1g_redundancy.png
--- a/ip_cores/.gitignore
+++ b/ip_cores/.gitignore
+wr-hdl
+general-cores
--- a/general-cores @ 17d08e59
+++ b/general-cores @ 17d08e59
+Subproject commit 17d08e592c482848bf1ce9401f39a2a8749d04f4
--- a/wr-cores @ 19117f27
+++ b/wr-cores @ 19117f27
+Subproject commit 19117f273963055a1d05353a5cd1e68882624eec
--- a/ip_cores/wr-cores-local/.gitignore
+++ b/ip_cores/wr-cores-local/.gitignore
+*.*\#
+\#*
+.\#*
+*.*~
+syn/
+work
+*.wlf
+modelsim.ini
+transcript
+*.vstf
+*.bak
+*.vcd
+*.h
+doc/
+*.o
+*.bin
+*.elf
+*.ucdb
+Makefile
+*.xml
+xgui/
--- a/ip_cores/wr-cores-local/Manifest.py
+++ b/ip_cores/wr-cores-local/Manifest.py
+modules =  {
+    "local" : [
+        "modules",
+        "platform",
+        "board",
+    ],
+}
--- a/ip_cores/wr-cores-local/bin/wrpc/wrc_phy16.bram
+++ b/ip_cores/wr-cores-local/bin/wrpc/wrc_phy16.bram
--- a/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8.bram
+++ b/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8.bram
--- a/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8.mif
+++ b/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8.mif
--- a/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8_sim.bram
+++ b/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8_sim.bram
--- a/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8_sim.mif
+++ b/ip_cores/wr-cores-local/bin/wrpc/wrc_phy8_sim.mif
--- a/ip_cores/wr-cores-local/board/Manifest.py
+++ b/ip_cores/wr-cores-local/board/Manifest.py
+try:
+    if board in ["spec", "svec", "vfchd", "common"]:
+        modules = {"local" : [ board ] }
+except NameError:
+    pass
--- a/ip_cores/wr-cores-local/board/clbv2/Manifest.py
+++ b/ip_cores/wr-cores-local/board/clbv2/Manifest.py
+files = [
+    "wr_clbv2_pkg.vhd",
+    "xwrc_board_clbv2.vhd",
+    "wrc_board_clbv2.vhd",
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/ip_cores/wr-cores-local/board/clbv2/wr_clbv2_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/clbv2/wr_clbv2_pkg.vhd
--- a/ip_cores/wr-cores-local/board/clbv2/wrc_board_clbv2.vhd
+++ b/ip_cores/wr-cores-local/board/clbv2/wrc_board_clbv2.vhd
--- a/ip_cores/wr-cores-local/board/clbv2/xwrc_board_clbv2.vhd
+++ b/ip_cores/wr-cores-local/board/clbv2/xwrc_board_clbv2.vhd
--- a/ip_cores/wr-cores-local/board/clbv3/Manifest.py
+++ b/ip_cores/wr-cores-local/board/clbv3/Manifest.py
+files = [
+    "wr_clbv3_pkg.vhd",
+    "xwrc_board_clbv3.vhd",
+    "wrc_board_clbv3.vhd",
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/ip_cores/wr-cores-local/board/clbv3/wr_clbv3_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/clbv3/wr_clbv3_pkg.vhd
--- a/ip_cores/wr-cores-local/board/clbv3/wrc_board_clbv3.vhd
+++ b/ip_cores/wr-cores-local/board/clbv3/wrc_board_clbv3.vhd
--- a/ip_cores/wr-cores-local/board/clbv3/xwrc_board_clbv3.vhd
+++ b/ip_cores/wr-cores-local/board/clbv3/xwrc_board_clbv3.vhd
--- a/ip_cores/wr-cores-local/board/common/Manifest.py
+++ b/ip_cores/wr-cores-local/board/common/Manifest.py
+files = [
+    "wr_board_pkg.vhd",
+    "xwrc_board_common.vhd",
+]
--- a/ip_cores/wr-cores-local/board/common/wr_board_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/common/wr_board_pkg.vhd
--- a/ip_cores/wr-cores-local/board/common/xwrc_board_common.vhd
+++ b/ip_cores/wr-cores-local/board/common/xwrc_board_common.vhd
--- a/ip_cores/wr-cores-local/board/cute/Manifest.py
+++ b/ip_cores/wr-cores-local/board/cute/Manifest.py
+files = [
+    "wr_cute_pkg.vhd",
+    "xwrc_board_cute.vhd",
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/ip_cores/wr-cores-local/board/cute/wr_cute_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/cute/wr_cute_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for CUTE package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_cute_pkg.vhd
+-- Author(s)  : Hongming Li <lihm.thu@foxmail.com>
+-- Company    : Tsinghua Univ. (DEP)
+-- Created    : 2018-07-14
+-- Last update: 2018-07-14
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_cute_pkg is
+
+  component xwrc_board_cute is
+    generic(
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := false;
+      g_aux_clks                  : integer              := 0;
+      g_fabric_iface              : t_board_fabric_iface := plain;
+      g_streamers_op_mode         : t_streamers_op_mode  := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params := c_rx_streamer_params_defaut;
+      g_aux_sdb                   : t_sdb_device         := c_wrc_periph3_sdb;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_diag_id                   : integer              := 0;
+      g_diag_ver                  : integer              := 0;
+      g_diag_ro_size              : integer              := 0;
+      g_diag_rw_size              : integer              := 0;
+      -- CUTE special
+      g_cute_version              : string               := "2.2";
+      g_sfp0_enable               : integer              := 1;
+      g_sfp1_enable               : integer              := 0;
+      g_phy_refclk_sel            : integer              := 0;
+      g_multiboot_enable          : boolean              := false);
+    port (
+      areset_n_i          : in  std_logic;
+      areset_edge_n_i     : in  std_logic := '1';
+      clk_20m_vcxo_i      : in  std_logic;
+      clk_125m_pllref_p_i : in  std_logic;
+      clk_125m_pllref_n_i : in  std_logic;
+      clk_125m_gtp0_p_i   : in  std_logic :='0';
+      clk_125m_gtp0_n_i   : in  std_logic :='0';
+      clk_125m_gtp1_p_i   : in  std_logic :='0';
+      clk_125m_gtp1_n_i   : in  std_logic :='0';
+      clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_10m_ext_i       : in  std_logic                               := '0';
+      pps_ext_i           : in  std_logic                               := '0';
+      clk_sys_62m5_o      : out std_logic;
+      clk_ref_125m_o      : out std_logic;
+      clk_10m_ext_o       : out std_logic;
+      rst_sys_62m5_n_o    : out std_logic;
+      rst_ref_125m_n_o    : out std_logic;
+      plldac_sclk_o       : out std_logic;
+      plldac_din_o        : out std_logic;
+      plldac_clr_n_o      : out std_logic;
+      plldac_load_n_o     : out std_logic;
+      plldac_sync_n_o     : out std_logic;
+      sfp0_txp_o          : out std_logic;
+      sfp0_txn_o          : out std_logic;
+      sfp0_rxp_i          : in  std_logic := '0';
+      sfp0_rxn_i          : in  std_logic := '0';
+      sfp0_det_i          : in  std_logic := '0';
+      sfp0_sda_i          : in  std_logic := '1';
+      sfp0_sda_o          : out std_logic;
+      sfp0_scl_i          : in  std_logic := '1';
+      sfp0_scl_o          : out std_logic;
+      sfp0_rate_select_o  : out std_logic;
+      sfp0_tx_fault_i     : in  std_logic := '0';
+      sfp0_tx_disable_o   : out std_logic;
+      sfp0_los_i          : in  std_logic := '0';
+      sfp1_txp_o          : out std_logic;
+      sfp1_txn_o          : out std_logic;
+      sfp1_rxp_i          : in  std_logic := '0';
+      sfp1_rxn_i          : in  std_logic := '0';
+      sfp1_det_i          : in  std_logic := '0';
+      sfp1_sda_i          : in  std_logic := '1';
+      sfp1_sda_o          : out std_logic;
+      sfp1_scl_i          : in  std_logic := '1';
+      sfp1_scl_o          : out std_logic;
+      sfp1_rate_select_o  : out std_logic;
+      sfp1_tx_fault_i     : in  std_logic := '0';
+      sfp1_tx_disable_o   : out std_logic;
+      sfp1_los_i          : in  std_logic := '0';
+      eeprom_sda_i        : in  std_logic := '1';
+      eeprom_sda_o        : out std_logic;
+      eeprom_scl_i        : in  std_logic := '1';
+      eeprom_scl_o        : out std_logic;
+      onewire_i           : in  std_logic;
+      onewire_oen_o       : out std_logic;
+      uart_rxd_i          : in  std_logic;
+      uart_txd_o          : out std_logic;
+      flash_sclk_o        : out std_logic;
+      flash_ncs_o         : out std_logic;
+      flash_mosi_o        : out std_logic;
+      flash_miso_i        : in  std_logic := '1';
+      wb_slave_o          : out t_wishbone_slave_out;
+      wb_slave_i          : in  t_wishbone_slave_in := cc_dummy_slave_in;
+      aux_master_o        : out t_wishbone_master_out;
+      aux_master_i        : in  t_wishbone_master_in := cc_dummy_master_in;
+      wrf_src_o           : out t_wrf_source_out;
+      wrf_src_i           : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o           : out t_wrf_sink_out;
+      wrf_snk_i           : in  t_wrf_sink_in   := c_dummy_snk_in;
+      wrs_tx_data_i       : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i      : in  std_logic                                        := '0';
+      wrs_tx_dreq_o       : out std_logic;
+      wrs_tx_last_i       : in  std_logic                                        := '1';
+      wrs_tx_flush_i      : in  std_logic                                        := '0';
+      wrs_tx_cfg_i        : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+      wrs_rx_first_o      : out std_logic;
+      wrs_rx_last_o       : out std_logic;
+      wrs_rx_data_o       : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o      : out std_logic;
+      wrs_rx_dreq_i       : in  std_logic                                        := '0';
+      wrs_rx_cfg_i        : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+      wb_eth_master_o     : out t_wishbone_master_out;
+      wb_eth_master_i     : in  t_wishbone_master_in := cc_dummy_master_in;
+      aux_diag_i          : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+      aux_diag_o          : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+      timestamps_o         : out t_txtsu_timestamp;
+      timestamps_ack_i     : in  std_logic := '1';
+      abscal_txts_o        : out std_logic;
+      abscal_rxts_o        : out std_logic;
+      fc_tx_pause_req_i    : in  std_logic                     := '0';
+      fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      tm_link_up_o         : out std_logic;
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      led_act_o            : out std_logic;
+      led_link_o           : out std_logic;
+      btn1_i               : in  std_logic := '1';
+      btn2_i               : in  std_logic := '1';
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+      pps_csync_o          : out std_logic;
+      link_ok_o            : out std_logic);
+  end component xwrc_board_cute;
+
+  constant c_xwb_tcpip_sdb : t_sdb_device := (
+      abi_class     => x"0000",              -- undocumented device
+      abi_ver_major => x"01",
+      abi_ver_minor => x"01",
+      wbd_endian    => c_sdb_endian_big,
+      wbd_width     => x"4",                 -- 8/16/32-bit port granularity
+      sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+      vendor_id => x"0000000000001103",  -- thu
+      device_id => x"c0413599",
+      version   => x"00000001",
+      date      => x"20160424",
+      name      => "wr-tcp-ip-stack    ")));
+
+end wr_cute_pkg;
--- a/ip_cores/wr-cores-local/board/cute/xwrc_board_cute.vhd
+++ b/ip_cores/wr-cores-local/board/cute/xwrc_board_cute.vhd
--- a/ip_cores/wr-cores-local/board/fasec/Manifest.py
+++ b/ip_cores/wr-cores-local/board/fasec/Manifest.py
+files = [
+    "wr_fasec_pkg.vhd",
+    "xwrc_board_fasec.vhd",
+    "wrc_board_fasec.vhd",
+    "wrc_board_fasec_ip.xdc"
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/ip_cores/wr-cores-local/board/fasec/wr_fasec_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/fasec/wr_fasec_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for FASEC package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_fasec_pkg.vhd
+-- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-08-02
+-- Last update: 2017-09-07
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2017 CERN
+--
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_fasec_pkg is
+
+  component xwrc_board_fasec
+    generic(
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_aux_clks                  : integer              := 0;
+      g_fabric_iface              : t_board_fabric_iface := plain;
+      g_streamers_op_mode         : t_streamers_op_mode  := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params := c_rx_streamer_params_defaut;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_diag_id                   : integer              := 0;
+      g_diag_ver                  : integer              := 0;
+      g_diag_ro_size              : integer              := 0;
+      g_diag_rw_size              : integer              := 0);
+    port (
+      areset_n_i          : in  std_logic;
+      areset_edge_n_i     : in  std_logic := '1';
+      clk_20m_vcxo_i      : in  std_logic;
+      clk_125m_pllref_p_i : in  std_logic;
+      clk_125m_pllref_n_i : in  std_logic;
+      clk_125m_gtp_n_i    : in  std_logic;
+      clk_125m_gtp_p_i    : in  std_logic;
+      clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_10m_ext_i       : in  std_logic                               := '0';
+      pps_ext_i           : in  std_logic                               := '0';
+      clk_sys_62m5_o      : out std_logic;
+      clk_ref_125m_o      : out std_logic;
+      rst_sys_62m5_n_o    : out std_logic;
+      rst_ref_125m_n_o    : out std_logic;
+  
+      plldac_sclk_o   : out std_logic;
+      plldac_din_o    : out std_logic;
+      pll25dac_cs_n_o : out std_logic;
+      pll20dac_cs_n_o : out std_logic;
+  
+      sfp_txp_o         : out std_logic;
+      sfp_txn_o         : out std_logic;
+      sfp_rxp_i         : in  std_logic;
+      sfp_rxn_i         : in  std_logic;
+      sfp_det_i         : in  std_logic := '1';
+      sfp_sda_i         : in  std_logic;
+      sfp_sda_o         : out std_logic;
+      sfp_sda_t         : out std_logic;
+      sfp_scl_i         : in  std_logic;
+      sfp_scl_o         : out std_logic;
+      sfp_scl_t         : out std_logic;
+      sfp_rate_select_o : out std_logic;
+      sfp_tx_fault_i    : in  std_logic := '0';
+      sfp_tx_disable_o  : out std_logic;
+      sfp_los_i         : in  std_logic := '0';
+  
+      eeprom_sda_i : in  std_logic;
+      eeprom_sda_o : out std_logic;
+      eeprom_sda_t : out std_logic;
+      eeprom_scl_i : in  std_logic;
+      eeprom_scl_o : out std_logic;
+      eeprom_scl_t : out std_logic;
+    
+      thermo_id_i : in  std_logic;
+      thermo_id_o : out std_logic;
+      thermo_id_t : out std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic;
+  
+      flash_sclk_o : out std_logic;
+      flash_ncs_o  : out std_logic;
+      flash_mosi_o : out std_logic;
+      flash_miso_i : in  std_logic := '0';
+  
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      s00_axi_aclk_o  : out std_logic;
+      s00_axi_aresetn : in  std_logic;
+      s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+      s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+      s00_axi_awvalid : in  std_logic;
+      s00_axi_awready : out std_logic;
+      s00_axi_wdata   : in std_logic_vector(31 downto 0);
+      s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+      s00_axi_wvalid  : in  std_logic;
+      s00_axi_wready  : out std_logic;
+      s00_axi_bresp   : out std_logic_vector(1 downto 0);
+      s00_axi_bvalid  : out std_logic;
+      s00_axi_bready  : in std_logic;
+      s00_axi_araddr  : in std_logic_vector(31 downto 0);
+      s00_axi_arprot  : in std_logic_vector(2 downto 0);
+      s00_axi_arvalid : in std_logic;
+      s00_axi_arready : out std_logic;
+      s00_axi_rdata   : out std_logic_vector(31 downto 0);
+      s00_axi_rresp   : out std_logic_vector(1 downto 0);
+      s00_axi_rvalid  : out std_logic;
+      s00_axi_rready  : in std_logic;
+      s00_axi_rlast   : out std_logic;
+      axi_int_o       : out std_logic;
+  
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+  
+      wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i : in  std_logic                                        := '0';
+      wrs_tx_dreq_o  : out std_logic;
+      wrs_tx_last_i  : in  std_logic                                        := '1';
+      wrs_tx_flush_i : in  std_logic                                        := '0';
+      wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+      wrs_rx_first_o : out std_logic;
+      wrs_rx_last_o  : out std_logic;
+      wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o : out std_logic;
+      wrs_rx_dreq_i  : in  std_logic                                        := '0';
+      wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+
+      wb_eth_master_o : out t_wishbone_master_out;
+      wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+  
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+  
+      timestamps_o     : out t_txtsu_timestamp;
+      timestamps_ack_i : in  std_logic := '1';
+  
+      abscal_txts_o       : out std_logic;
+      abscal_rxts_o       : out std_logic;
+  
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+  
+      tm_link_up_o    : out std_logic;
+      tm_time_valid_o : out std_logic;
+      tm_tai_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+  
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      btn1_i     : in  std_logic := '1';
+      btn2_i     : in  std_logic := '1';
+      pps_p_o    : out std_logic;
+      pps_led_o  : out std_logic;
+      link_ok_o  : out std_logic);
+  end component xwrc_board_fasec;
+
+end wr_fasec_pkg;
--- a/ip_cores/wr-cores-local/board/fasec/wrc_board_fasec.vhd
+++ b/ip_cores/wr-cores-local/board/fasec/wrc_board_fasec.vhd
--- a/ip_cores/wr-cores-local/board/fasec/wrc_board_fasec_ip.xdc
+++ b/ip_cores/wr-cores-local/board/fasec/wrc_board_fasec_ip.xdc
--- a/ip_cores/wr-cores-local/board/fasec/wrc_board_fasec_v4_1.tcl
+++ b/ip_cores/wr-cores-local/board/fasec/wrc_board_fasec_v4_1.tcl
--- a/ip_cores/wr-cores-local/board/fasec/xwrc_board_fasec.vhd
+++ b/ip_cores/wr-cores-local/board/fasec/xwrc_board_fasec.vhd
--- a/ip_cores/wr-cores-local/board/spec/Manifest.py
+++ b/ip_cores/wr-cores-local/board/spec/Manifest.py
--- a/ip_cores/wr-cores-local/board/spec/wr_spec_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/spec/wr_spec_pkg.vhd
--- a/ip_cores/wr-cores-local/board/spec/wrc_board_spec.vhd
+++ b/ip_cores/wr-cores-local/board/spec/wrc_board_spec.vhd
--- a/ip_cores/wr-cores-local/board/spec/xwrc_board_spec.vhd
+++ b/ip_cores/wr-cores-local/board/spec/xwrc_board_spec.vhd
--- a/ip_cores/wr-cores-local/board/svec/Manifest.py
+++ b/ip_cores/wr-cores-local/board/svec/Manifest.py
--- a/ip_cores/wr-cores-local/board/svec/wr_svec_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/svec/wr_svec_pkg.vhd
--- a/ip_cores/wr-cores-local/board/svec/wrc_board_svec.vhd
+++ b/ip_cores/wr-cores-local/board/svec/wrc_board_svec.vhd
--- a/ip_cores/wr-cores-local/board/svec/xwrc_board_svec.vhd
+++ b/ip_cores/wr-cores-local/board/svec/xwrc_board_svec.vhd
--- a/ip_cores/wr-cores-local/board/vfchd/Manifest.py
+++ b/ip_cores/wr-cores-local/board/vfchd/Manifest.py
--- a/ip_cores/wr-cores-local/board/vfchd/sfp_i2c_adapter.vhd
+++ b/ip_cores/wr-cores-local/board/vfchd/sfp_i2c_adapter.vhd
--- a/ip_cores/wr-cores-local/board/vfchd/wr_vfchd_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/vfchd/wr_vfchd_pkg.vhd
--- a/ip_cores/wr-cores-local/board/vfchd/wrc_board_vfchd.vhd
+++ b/ip_cores/wr-cores-local/board/vfchd/wrc_board_vfchd.vhd
--- a/ip_cores/wr-cores-local/board/vfchd/xwrc_board_vfchd.vhd
+++ b/ip_cores/wr-cores-local/board/vfchd/xwrc_board_vfchd.vhd
--- a/ip_cores/wr-cores-local/board/vxs/Manifest.py
+++ b/ip_cores/wr-cores-local/board/vxs/Manifest.py
--- a/ip_cores/wr-cores-local/board/vxs/wr_vxs_pkg.vhd
+++ b/ip_cores/wr-cores-local/board/vxs/wr_vxs_pkg.vhd
--- a/ip_cores/wr-cores-local/board/vxs/wrc_board_vxs.vhd
+++ b/ip_cores/wr-cores-local/board/vxs/wrc_board_vxs.vhd
--- a/ip_cores/wr-cores-local/board/vxs/xwrc_board_vxs.vhd
+++ b/ip_cores/wr-cores-local/board/vxs/xwrc_board_vxs.vhd
--- a/ip_cores/wr-cores-local/modules/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/Manifest.py
--- a/ip_cores/wr-cores-local/modules/fabric/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/fabric/Manifest.py
--- a/ip_cores/wr-cores-local/modules/fabric/wr_fabric_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/wr_fabric_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwb_fabric_sink.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwb_fabric_sink.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwb_fabric_source.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwb_fabric_source.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/lbk_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/lbk_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/lbk_wishbone.wb
+++ b/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/lbk_wishbone.wb
--- a/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/wrf_loopback.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/wrf_loopback.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/xwrf_loopback.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwrf_loopback/xwrf_loopback.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwrf_mux.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwrf_mux.vhd
--- a/ip_cores/wr-cores-local/modules/fabric/xwrf_reg.vhd
+++ b/ip_cores/wr-cores-local/modules/fabric/xwrf_reg.vhd
--- a/ip_cores/wr-cores-local/modules/timing/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/timing/Manifest.py
--- a/ip_cores/wr-cores-local/modules/timing/dmtd_phase_meas.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/dmtd_phase_meas.vhd
--- a/ip_cores/wr-cores-local/modules/timing/dmtd_with_deglitcher.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/dmtd_with_deglitcher.vhd
--- a/ip_cores/wr-cores-local/modules/timing/hpll_period_detect.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/hpll_period_detect.vhd
--- a/ip_cores/wr-cores-local/modules/timing/multi_dmtd_with_deglitcher.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/multi_dmtd_with_deglitcher.vhd
--- a/ip_cores/wr-cores-local/modules/timing/oserdes_4_to_1.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/oserdes_4_to_1.vhd
--- a/ip_cores/wr-cores-local/modules/timing/pulse_gen.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/pulse_gen.vhd
--- a/ip_cores/wr-cores-local/modules/timing/pulse_stamper.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/pulse_stamper.vhd
--- a/ip_cores/wr-cores-local/modules/timing/pulse_stamper_sync.vhd
+++ b/ip_cores/wr-cores-local/modules/timing/pulse_stamper_sync.vhd
--- a/ip_cores/wr-cores-local/modules/wr_dacs/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_dacs/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_dacs/cute_serial_dac.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_dacs/cute_serial_dac.vhd
--- a/ip_cores/wr-cores-local/modules/wr_dacs/cute_serial_dac_arb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_dacs/cute_serial_dac_arb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_dacs/spec_serial_dac.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_dacs/spec_serial_dac.vhd
--- a/ip_cores/wr-cores-local/modules/wr_dacs/spec_serial_dac_arb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_dacs/spec_serial_dac_arb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/.gitignore
+++ b/ip_cores/wr-cores-local/modules/wr_eca/.gitignore
--- a/ip_cores/wr-cores-local/modules/wr_eca/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_eca/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca-ctl.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca-ctl.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca-table.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca-table.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_ac_wbm.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_ac_wbm.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_ac_wbm_auto.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_ac_wbm_auto.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_adder.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_adder.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_auto.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_auto.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_auto_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_auto_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic_helper.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic_helper.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic_swap.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic_swap.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_bitonic_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_channel.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_channel.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_channel_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_channel_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_compact.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_compact.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_compact_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_compact_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_data.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_data.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_fifo.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_fifo.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_fifo_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_fifo_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_free.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_free.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_free_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_free_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_internals_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_internals_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_msi.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_msi.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_offset.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_offset.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_piso_fifo.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_piso_fifo.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_piso_fifo_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_piso_fifo_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_queue.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_queue.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_queue_auto.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_queue_auto.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_queue_auto_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_queue_auto_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_rmw.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_rmw.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_rmw_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_rmw_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_scan.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_scan.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_scan_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_scan_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_scubus_channel.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_scubus_channel.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_sdp.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_sdp.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_search.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_search.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tag_channel.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tag_channel.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tag_channel_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tag_channel_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tdp.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tdp.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu_auto.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu_auto.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu_auto_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu_auto_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu_fsm.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_tlu_fsm.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_walker.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_walker.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_wb_event.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_wb_event.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/eca_wr_time.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/eca_wr_time.vhd
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-channel.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-channel.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-eca.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-eca.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-queue.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-queue.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-stream.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/hw-stream.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/load-table.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/load-table.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/probe-eca.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/probe-eca.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/store-table.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/store-table.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/table.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/table.cpp
--- a/ip_cores/wr-cores-local/modules/wr_eca/lib/version.h.in
+++ b/ip_cores/wr-cores-local/modules/wr_eca/lib/version.h.in
--- a/ip_cores/wr-cores-local/modules/wr_eca/sim.sh
+++ b/ip_cores/wr-cores-local/modules/wr_eca/sim.sh
--- a/ip_cores/wr-cores-local/modules/wr_eca/wave.gtkw
+++ b/ip_cores/wr-cores-local/modules/wr_eca/wave.gtkw
--- a/ip_cores/wr-cores-local/modules/wr_eca/wr_eca.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_eca/wr_eca.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_private_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_private_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_1000basex_pcs.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_1000basex_pcs.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_autonegotiation.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_autonegotiation.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_crc32_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_crc32_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_flow_control.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_flow_control.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_leds_controller.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_leds_controller.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_packet_filter.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_packet_filter.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_registers_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_registers_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rmon_counters.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rmon_counters.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rtu_header_extract.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rtu_header_extract.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_buffer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_buffer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_bypass_queue.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_bypass_queue.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_crc_size_check.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_crc_size_check.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_early_address_match.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_early_address_match.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_oob_insert.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_oob_insert.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_path.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_path.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_vlan_unit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_vlan_unit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_wb_master.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_wb_master.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_sync_detect.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_sync_detect.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_sync_detect_16bit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_sync_detect_16bit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_timestamping_unit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_timestamping_unit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_ts_counter.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_ts_counter.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_crc_inserter.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_crc_inserter.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_framer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_framer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_header_processor.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_header_processor.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_packet_injection.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_packet_injection.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_path.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_path.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_vlan_unit.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_vlan_unit.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_wishbone_controller.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_wishbone_controller.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/ep_wishbone_controller.wb
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/ep_wishbone_controller.wb
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/pcs_regs.wb
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/pcs_regs.wb
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/wr_endpoint.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/wr_endpoint.vhd
--- a/ip_cores/wr-cores-local/modules/wr_endpoint/xwr_endpoint.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_endpoint/xwr_endpoint.vhd
--- a/ip_cores/wr-cores-local/modules/wr_mini_nic/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_mini_nic/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_mini_nic/mini_nic.wb
+++ b/ip_cores/wr-cores-local/modules/wr_mini_nic/mini_nic.wb
--- a/ip_cores/wr-cores-local/modules/wr_mini_nic/minic_packet_buffer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_mini_nic/minic_packet_buffer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_mini_nic/minic_wb_slave.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_mini_nic/minic_wb_slave.vhd
--- a/ip_cores/wr-cores-local/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_mini_nic/wr_mini_nic.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_mini_nic/wr_mini_nic.vhd
--- a/ip_cores/wr-cores-local/modules/wr_mini_nic/xwr_mini_nic.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_mini_nic/xwr_mini_nic.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_nic/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_buffer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_buffer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_bw_throttling.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_bw_throttling.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_constants_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_constants_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_descriptor_manager.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_descriptor_manager.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_descriptors_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_descriptors_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_elastic_buffer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_elastic_buffer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_rx_fsm.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_rx_fsm.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_tx_fsm.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_tx_fsm.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_wbgen2_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_wbgen2_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/nic_wishbone_slave.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/nic_wishbone_slave.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/wr_nic.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/wr_nic.vhd
--- a/ip_cores/wr-cores-local/modules/wr_nic/wr_nic.wb
+++ b/ip_cores/wr-cores-local/modules/wr_nic/wr_nic.wb
--- a/ip_cores/wr-cores-local/modules/wr_nic/xwr_nic.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_nic/xwr_nic.vhd
--- a/ip_cores/wr-cores-local/modules/wr_pps_gen/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_pps_gen/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_pps_gen/pps_gen_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_pps_gen/pps_gen_wb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_pps_gen/pps_gen_wb.wb
+++ b/ip_cores/wr-cores-local/modules/wr_pps_gen/pps_gen_wb.wb
--- a/ip_cores/wr-cores-local/modules/wr_pps_gen/wr_pps_gen.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_pps_gen/wr_pps_gen.vhd
--- a/ip_cores/wr-cores-local/modules/wr_pps_gen/xwr_pps_gen.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_pps_gen/xwr_pps_gen.vhd
--- a/ip_cores/wr-cores-local/modules/wr_si57x_interface/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_si57x_interface/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_si57x_interface/si570_if_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_si57x_interface/si570_if_wb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_si57x_interface/si570_if_wb.wb
+++ b/ip_cores/wr-cores-local/modules/wr_si57x_interface/si570_if_wb.wb
--- a/ip_cores/wr-cores-local/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_si57x_interface/wr_si57x_interface.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_si57x_interface/wr_si57x_interface.vhd
--- a/ip_cores/wr-cores-local/modules/wr_si57x_interface/xwr_si57x_interface.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_si57x_interface/xwr_si57x_interface.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/softpll_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/softpll_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_aligner.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_aligner.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_bangbang_pd.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_bangbang_pd.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_period_detect.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_period_detect.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_wb_slave.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_wb_slave.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_wb_slave.wb
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_wb_slave.wb
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/wr_softpll_ng.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/wr_softpll_ng.vhd
--- a/ip_cores/wr-cores-local/modules/wr_softpll_ng/xwr_softpll_ng.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_softpll_ng/xwr_softpll_ng.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_streamers/dropping_buffer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/dropping_buffer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/escape_detector.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/escape_detector.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/escape_inserter.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/escape_inserter.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/fifo_showahead_adapter.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/fifo_showahead_adapter.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/fixed_latency_delay.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/fixed_latency_delay.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/fixed_latency_ts_match.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/fixed_latency_ts_match.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/rx_streamer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/rx_streamer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/streamers_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/streamers_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/streamers_priv_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/streamers_priv_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/ts_restore_tai.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/ts_restore_tai.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/tx_streamer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/tx_streamer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wb.html
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wb.html
--- a/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wb.wb
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wb.wb
--- a/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/xrtx_streamers_stats.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/xrtx_streamers_stats.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/xrx_streamer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/xrx_streamer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/xrx_streamers_stats.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/xrx_streamers_stats.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/xtx_streamer.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/xtx_streamer.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/xtx_streamers_stats.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/xtx_streamers_stats.vhd
--- a/ip_cores/wr-cores-local/modules/wr_streamers/xwr_streamers.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_streamers/xwr_streamers.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tbi_phy/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_tbi_phy/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_tbi_phy/dec_8b10b.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tbi_phy/dec_8b10b.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tbi_phy/disparity_gen_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tbi_phy/disparity_gen_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tbi_phy/enc_8b10b.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tbi_phy/enc_8b10b.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tbi_phy/wr_tbi_phy.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tbi_phy/wr_tbi_phy.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tlu/.gitignore
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/.gitignore
--- a/ip_cores/wr-cores-local/modules/wr_tlu/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_tlu/lib/tlu.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/lib/tlu.cpp
--- a/ip_cores/wr-cores-local/modules/wr_tlu/tlu-ctl.cpp
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/tlu-ctl.cpp
--- a/ip_cores/wr-cores-local/modules/wr_tlu/tlu.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/tlu.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tlu/tlu_fsm.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/tlu_fsm.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tlu/tlu_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/tlu_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_tlu/tlu_tb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_tlu/tlu_tb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_txtsu/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wr_txtsu/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wr_txtsu/wr_txtsu.wb
+++ b/ip_cores/wr-cores-local/modules/wr_txtsu/wr_txtsu.wb
--- a/ip_cores/wr-cores-local/modules/wr_txtsu/wr_txtsu_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_txtsu/wr_txtsu_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wr_txtsu/wr_txtsu_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_txtsu/wr_txtsu_wb.vhd
--- a/ip_cores/wr-cores-local/modules/wr_txtsu/xwr_txtsu.vhd
+++ b/ip_cores/wr-cores-local/modules/wr_txtsu/xwr_txtsu.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/Manifest.py
+++ b/ip_cores/wr-cores-local/modules/wrc_core/Manifest.py
--- a/ip_cores/wr-cores-local/modules/wrc_core/wr_core.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wr_core.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrc_diags_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrc_diags_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrc_diags_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrc_diags_wb.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrc_diags_wb.wb
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrc_diags_wb.wb
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrc_periph.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrc_periph.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrc_syscon_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrc_syscon_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrc_syscon_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrc_syscon_wb.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrc_syscon_wb.wb
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrc_syscon_wb.wb
--- a/ip_cores/wr-cores-local/modules/wrc_core/wrcore_pkg.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/wrcore_pkg.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/xwr_core.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/xwr_core.vhd
--- a/ip_cores/wr-cores-local/modules/wrc_core/xwrc_diags_wb.vhd
+++ b/ip_cores/wr-cores-local/modules/wrc_core/xwrc_diags_wb.vhd
--- a/ip_cores/wr-cores-local/platform/Manifest.py
+++ b/ip_cores/wr-cores-local/platform/Manifest.py
--- a/ip_cores/wr-cores-local/platform/altera/Manifest.py
+++ b/ip_cores/wr-cores-local/platform/altera/Manifest.py
--- a/ip_cores/wr-cores-local/platform/altera/wr_altera_pkg.vhd
+++ b/ip_cores/wr-cores-local/platform/altera/wr_altera_pkg.vhd
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/.gitignore
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/.gitignore
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/Manifest.py
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/Manifest.py
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/arria2_phy.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/arria2_phy.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/arria2_phy_reconf.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/arria2_phy_reconf.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/wr_arria2_phy.qip
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/wr_arria2_phy.qip
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/wr_arria2_phy.tcl
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/wr_arria2_phy.tcl
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/Manifest.py
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/Manifest.py
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/arria5_phy16.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/arria5_phy16.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/arria5_phy8.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/arria5_phy8.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/arria5_phy_reconf.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/arria5_phy_reconf.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/arria5_dmtd_pll_default.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/arria5_dmtd_pll_default.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/arria5_ext_ref_pll_default.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/arria5_ext_ref_pll_default.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/arria5_sys_pll_default.txt
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/arria5_sys_pll_default.txt
--- a/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/wr_arria5_pll_default.tcl
+++ b/ip_cores/wr-cores-local/platform/altera/wr_arria5_pll_default/wr_arria5_pll_default.tcl
--- a/ip_cores/wr-cores-local/platform/altera/xwrc_platform_altera.vhd
+++ b/ip_cores/wr-cores-local/platform/altera/xwrc_platform_altera.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/Manifest.py
+++ b/ip_cores/wr-cores-local/platform/xilinx/Manifest.py
--- a/ip_cores/wr-cores-local/platform/xilinx/chipscope/Manifest.py
+++ b/ip_cores/wr-cores-local/platform/xilinx/chipscope/Manifest.py
--- a/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_spartan6_icon.ngc
+++ b/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_spartan6_icon.ngc
--- a/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_spartan6_ila.ngc
+++ b/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_spartan6_ila.ngc
--- a/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_virtex5_icon.ngc
+++ b/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_virtex5_icon.ngc
--- a/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_virtex5_ila.ngc
+++ b/ip_cores/wr-cores-local/platform/xilinx/chipscope/chipscope_virtex5_ila.ngc
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/Manifest.py
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gt.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gt.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_sync_block.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_sync_block.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_family7.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_family7.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/gc_reset_synchronizer.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/gc_reset_synchronizer.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_phy_family7.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_phy_family7.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_reset.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_reset.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_rx_buffer_bypass.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_rx_buffer_bypass.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_tx_buffer_bypass.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_tx_buffer_bypass.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_wrapper.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_wrapper.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4-10gb/transceivers_10gb/.gitignore
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4-10gb/transceivers_10gb/.gitignore
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4-10gb/transceivers_10gb/transceivers_10gb.xci
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4-10gb/transceivers_10gb/transceivers_10gb.xci
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4/gtwizard_ultrascale_1/.gitignore
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4/gtwizard_ultrascale_1/.gitignore
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4/gtwizard_ultrascale_1/gtwizard_ultrascale_1.xci
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gthe4/gtwizard_ultrascale_1/gtwizard_ultrascale_1.xci
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex5/v5_gtp_align_detect.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex5/v5_gtp_align_detect.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex5/whiterabbit_gtp_wrapper_tile_virtex5.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex5/whiterabbit_gtp_wrapper_tile_virtex5.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex5/wr_gtp_phy_virtex5.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex5/wr_gtp_phy_virtex5.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/gtp_phase_align_virtex6.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/gtp_phase_align_virtex6.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/gtx_reset.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/gtx_reset.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/whiterabbitgtx_wrapper_gtx.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/whiterabbitgtx_wrapper_gtx.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/wr_gtx_phy_virtex6.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_gtp_phy/virtex6/wr_gtx_phy_virtex6.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/wr_xilinx_pkg.vhd
--- a/ip_cores/wr-cores-local/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/ip_cores/wr-cores-local/platform/xilinx/xwrc_platform_xilinx.vhd
--- a/ip_cores/wr-cores-local/sim/drivers/simdrv_minic.svh
+++ b/ip_cores/wr-cores-local/sim/drivers/simdrv_minic.svh
--- a/ip_cores/wr-cores-local/sim/drivers/simdrv_wr_endpoint.svh
+++ b/ip_cores/wr-cores-local/sim/drivers/simdrv_wr_endpoint.svh
--- a/ip_cores/wr-cores-local/sim/endpoint_mdio.v
+++ b/ip_cores/wr-cores-local/sim/endpoint_mdio.v
--- a/ip_cores/wr-cores-local/sim/endpoint_regs.v
+++ b/ip_cores/wr-cores-local/sim/endpoint_regs.v
--- a/ip_cores/wr-cores-local/sim/eth_packet.svh
+++ b/ip_cores/wr-cores-local/sim/eth_packet.svh
--- a/ip_cores/wr-cores-local/sim/fabric_emu/fabric_demo_tap.sv
+++ b/ip_cores/wr-cores-local/sim/fabric_emu/fabric_demo_tap.sv
--- a/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu.sv
+++ b/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu.sv
--- a/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_defs.sv
+++ b/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_defs.sv
--- a/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_demo.sv
+++ b/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_demo.sv
--- a/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_funcs.sv
+++ b/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_funcs.sv
--- a/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_tap.sv
+++ b/ip_cores/wr-cores-local/sim/fabric_emu/fabric_emu_tap.sv
--- a/ip_cores/wr-cores-local/sim/if_wb_classic_master.svh
+++ b/ip_cores/wr-cores-local/sim/if_wb_classic_master.svh
--- a/ip_cores/wr-cores-local/sim/if_wb_link.svh
+++ b/ip_cores/wr-cores-local/sim/if_wb_link.svh
--- a/ip_cores/wr-cores-local/sim/if_wb_master.svh
+++ b/ip_cores/wr-cores-local/sim/if_wb_master.svh
--- a/ip_cores/wr-cores-local/sim/if_wb_slave.svh
+++ b/ip_cores/wr-cores-local/sim/if_wb_slave.svh
--- a/ip_cores/wr-cores-local/sim/if_wishbone_accessor.svh
+++ b/ip_cores/wr-cores-local/sim/if_wishbone_accessor.svh
--- a/ip_cores/wr-cores-local/sim/if_wishbone_defs.svh
+++ b/ip_cores/wr-cores-local/sim/if_wishbone_defs.svh
--- a/ip_cores/wr-cores-local/sim/if_wishbone_types.svh
+++ b/ip_cores/wr-cores-local/sim/if_wishbone_types.svh
--- a/ip_cores/wr-cores-local/sim/lbk_regs.v
+++ b/ip_cores/wr-cores-local/sim/lbk_regs.v
--- a/ip_cores/wr-cores-local/sim/minic_regs.vh
+++ b/ip_cores/wr-cores-local/sim/minic_regs.vh
--- a/ip_cores/wr-cores-local/sim/nic_regs.vh
+++ b/ip_cores/wr-cores-local/sim/nic_regs.vh
--- a/ip_cores/wr-cores-local/sim/old_endpoint_regs.v
+++ b/ip_cores/wr-cores-local/sim/old_endpoint_regs.v
--- a/ip_cores/wr-cores-local/sim/pfilter.svh
+++ b/ip_cores/wr-cores-local/sim/pfilter.svh
--- a/ip_cores/wr-cores-local/sim/pps_gen_regs.v
+++ b/ip_cores/wr-cores-local/sim/pps_gen_regs.v
--- a/ip_cores/wr-cores-local/sim/simdrv_defs.svh
+++ b/ip_cores/wr-cores-local/sim/simdrv_defs.svh
--- a/ip_cores/wr-cores-local/sim/simdrv_txtsu.svh
+++ b/ip_cores/wr-cores-local/sim/simdrv_txtsu.svh
--- a/ip_cores/wr-cores-local/sim/simdrv_wr_nic.svh
+++ b/ip_cores/wr-cores-local/sim/simdrv_wr_nic.svh
--- a/ip_cores/wr-cores-local/sim/softpll_regs.v
+++ b/ip_cores/wr-cores-local/sim/softpll_regs.v
--- a/ip_cores/wr-cores-local/sim/softpll_regs_ng.vh
+++ b/ip_cores/wr-cores-local/sim/softpll_regs_ng.vh
--- a/ip_cores/wr-cores-local/sim/tbi_utils.sv
+++ b/ip_cores/wr-cores-local/sim/tbi_utils.sv
--- a/ip_cores/wr-cores-local/sim/txtsu_regs.vh
+++ b/ip_cores/wr-cores-local/sim/txtsu_regs.vh
--- a/ip_cores/wr-cores-local/sim/wb_fabric_defs.svh
+++ b/ip_cores/wr-cores-local/sim/wb_fabric_defs.svh
--- a/ip_cores/wr-cores-local/sim/wb_packet_sink.svh
+++ b/ip_cores/wr-cores-local/sim/wb_packet_sink.svh
--- a/ip_cores/wr-cores-local/sim/wb_packet_source.svh
+++ b/ip_cores/wr-cores-local/sim/wb_packet_source.svh
--- a/ip_cores/wr-cores-local/sim/wishbone_test_master.v
+++ b/ip_cores/wr-cores-local/sim/wishbone_test_master.v
--- a/ip_cores/wr-cores-local/sim/wr_streamers_wb.svh
+++ b/ip_cores/wr-cores-local/sim/wr_streamers_wb.svh
--- a/ip_cores/wr-cores-local/sim/wrc_diags_regs.vh
+++ b/ip_cores/wr-cores-local/sim/wrc_diags_regs.vh
--- a/ip_cores/wr-cores-local/sim/wrc_syscon_regs.vh
+++ b/ip_cores/wr-cores-local/sim/wrc_syscon_regs.vh
--- a/ip_cores/wr-cores-local/testbench/.gitignore
+++ b/ip_cores/wr-cores-local/testbench/.gitignore
--- a/ip_cores/wr-cores-local/testbench/mini_bone/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/mini_bone/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/mini_bone/main.sv
+++ b/ip_cores/wr-cores-local/testbench/mini_bone/main.sv
--- a/ip_cores/wr-cores-local/testbench/mini_bone/run.do
+++ b/ip_cores/wr-cores-local/testbench/mini_bone/run.do
--- a/ip_cores/wr-cores-local/testbench/mini_bone/wave.do
+++ b/ip_cores/wr-cores-local/testbench/mini_bone/wave.do
--- a/ip_cores/wr-cores-local/testbench/nic_bw_throttling/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/nic_bw_throttling/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/nic_bw_throttling/main.sv
+++ b/ip_cores/wr-cores-local/testbench/nic_bw_throttling/main.sv
--- a/ip_cores/wr-cores-local/testbench/nic_bw_throttling/run.do
+++ b/ip_cores/wr-cores-local/testbench/nic_bw_throttling/run.do
--- a/ip_cores/wr-cores-local/testbench/nic_bw_throttling/wave.do
+++ b/ip_cores/wr-cores-local/testbench/nic_bw_throttling/wave.do
--- a/ip_cores/wr-cores-local/testbench/top_level/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/top_level/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/top_level/NullFile
+++ b/ip_cores/wr-cores-local/testbench/top_level/NullFile
--- a/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/gn4124_bfm.svh
+++ b/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/gn4124_bfm.svh
--- a/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/gn412x_bfm.vhd
+++ b/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/gn412x_bfm.vhd
--- a/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/mem_model.vhd
+++ b/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/mem_model.vhd
--- a/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/textutil.vhd
+++ b/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/textutil.vhd
--- a/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/util.vhd
+++ b/ip_cores/wr-cores-local/testbench/top_level/gn4124_bfm/util.vhd
--- a/ip_cores/wr-cores-local/testbench/top_level/main.sv
+++ b/ip_cores/wr-cores-local/testbench/top_level/main.sv
--- a/ip_cores/wr-cores-local/testbench/top_level/run.do
+++ b/ip_cores/wr-cores-local/testbench/top_level/run.do
--- a/ip_cores/wr-cores-local/testbench/top_level/wave.do
+++ b/ip_cores/wr-cores-local/testbench/top_level/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/endpoint_phy_wrapper.svh
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/endpoint_phy_wrapper.svh
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/old_endpoint_wrapper.svh
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/old_endpoint_wrapper.svh
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/pcs_adapter.svh
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/pcs_adapter.svh
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/pfilter.svh
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/pfilter.svh
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/full_tb/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_endpoint_pkg.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_endpoint_pkg.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_dec_8b10b.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_dec_8b10b.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_enc_8b10b.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_enc_8b10b.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_pcs_tbi_mdio_wb.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_pcs_tbi_mdio_wb.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_crc_size_check.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_crc_size_check.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_wb_to_wrf.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_wb_to_wrf.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_wishbone_controller.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_wishbone_controller.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_wrf_to_wb.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_ep_wrf_to_wb.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
+++ b/ip_cores/wr-cores-local/testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
--- a/ip_cores/wr-cores-local/testbench/wr_fabric_reg/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_fabric_reg/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_minic/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_minic/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_minic/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_minic/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_minic/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_minic/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_minic/run_ci.do
+++ b/ip_cores/wr-cores-local/testbench/wr_minic/run_ci.do
--- a/ip_cores/wr-cores-local/testbench/wr_minic/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_minic/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/ep2ep_wrapper.svh
+++ b/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/ep2ep_wrapper.svh
--- a/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_minic_with_ep/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only-fixed-latency/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/tcl_stacktrace.txt
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/tcl_stacktrace.txt
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_basic-transfer/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers-only_multiword-transfer/wave.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/main.sv
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/run.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/run.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/run_ci.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/run_ci.do
--- a/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wr_streamers/streamers_multi_test/wave.do
--- a/ip_cores/wr-cores-local/testbench/wrc_core/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/wrc_core/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/wrc_core/functions.svh
+++ b/ip_cores/wr-cores-local/testbench/wrc_core/functions.svh
--- a/ip_cores/wr-cores-local/testbench/wrc_core/main.sv
+++ b/ip_cores/wr-cores-local/testbench/wrc_core/main.sv
--- a/ip_cores/wr-cores-local/testbench/wrc_core/run.do
+++ b/ip_cores/wr-cores-local/testbench/wrc_core/run.do
--- a/ip_cores/wr-cores-local/testbench/wrc_core/run_ci.do
+++ b/ip_cores/wr-cores-local/testbench/wrc_core/run_ci.do
--- a/ip_cores/wr-cores-local/testbench/wrc_core/wave.do
+++ b/ip_cores/wr-cores-local/testbench/wrc_core/wave.do
--- a/ip_cores/wr-cores-local/testbench/xwrf_loopback/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/xwrf_loopback/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/xwrf_loopback/functions.svh
+++ b/ip_cores/wr-cores-local/testbench/xwrf_loopback/functions.svh
--- a/ip_cores/wr-cores-local/testbench/xwrf_loopback/main.sv
+++ b/ip_cores/wr-cores-local/testbench/xwrf_loopback/main.sv
--- a/ip_cores/wr-cores-local/testbench/xwrf_loopback/run.do
+++ b/ip_cores/wr-cores-local/testbench/xwrf_loopback/run.do
--- a/ip_cores/wr-cores-local/testbench/xwrf_loopback/wave.do
+++ b/ip_cores/wr-cores-local/testbench/xwrf_loopback/wave.do
--- a/ip_cores/wr-cores-local/testbench/xwrf_mux/Manifest.py
+++ b/ip_cores/wr-cores-local/testbench/xwrf_mux/Manifest.py
--- a/ip_cores/wr-cores-local/testbench/xwrf_mux/main.sv
+++ b/ip_cores/wr-cores-local/testbench/xwrf_mux/main.sv
--- a/ip_cores/wr-cores-local/testbench/xwrf_mux/run.do
+++ b/ip_cores/wr-cores-local/testbench/xwrf_mux/run.do
--- a/ip_cores/wr-cores-local/testbench/xwrf_mux/wave.do
+++ b/ip_cores/wr-cores-local/testbench/xwrf_mux/wave.do
--- a/ip_cores/wr-cores-local/top/clbv2_ref_design/Manifest.py
+++ b/ip_cores/wr-cores-local/top/clbv2_ref_design/Manifest.py
--- a/ip_cores/wr-cores-local/top/clbv2_ref_design/clbv2_wr_ref_top.bmm
+++ b/ip_cores/wr-cores-local/top/clbv2_ref_design/clbv2_wr_ref_top.bmm
--- a/ip_cores/wr-cores-local/top/clbv2_ref_design/clbv2_wr_ref_top.ucf
+++ b/ip_cores/wr-cores-local/top/clbv2_ref_design/clbv2_wr_ref_top.ucf
--- a/ip_cores/wr-cores-local/top/clbv2_ref_design/clbv2_wr_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/clbv2_ref_design/clbv2_wr_ref_top.vhd
--- a/ip_cores/wr-cores-local/top/clbv3_ref_design/Manifest.py
+++ b/ip_cores/wr-cores-local/top/clbv3_ref_design/Manifest.py
--- a/ip_cores/wr-cores-local/top/clbv3_ref_design/clbv3_wr_ref_top.bmm
+++ b/ip_cores/wr-cores-local/top/clbv3_ref_design/clbv3_wr_ref_top.bmm
--- a/ip_cores/wr-cores-local/top/clbv3_ref_design/clbv3_wr_ref_top.ucf
+++ b/ip_cores/wr-cores-local/top/clbv3_ref_design/clbv3_wr_ref_top.ucf
--- a/ip_cores/wr-cores-local/top/clbv3_ref_design/clbv3_wr_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/clbv3_ref_design/clbv3_wr_ref_top.vhd
--- a/ip_cores/wr-cores-local/top/cute_ref_design/Manifest.py
+++ b/ip_cores/wr-cores-local/top/cute_ref_design/Manifest.py
--- a/ip_cores/wr-cores-local/top/cute_ref_design/cute_core_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/cute_ref_design/cute_core_ref_top.vhd
--- a/ip_cores/wr-cores-local/top/cute_ref_design/cute_wr_ref_top.ucf
+++ b/ip_cores/wr-cores-local/top/cute_ref_design/cute_wr_ref_top.ucf
--- a/ip_cores/wr-cores-local/top/cute_ref_design/cute_wr_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/cute_ref_design/cute_wr_ref_top.vhd
--- a/ip_cores/wr-cores-local/top/fasec_ref_design/fasec_ref_design.xdc
+++ b/ip_cores/wr-cores-local/top/fasec_ref_design/fasec_ref_design.xdc
--- a/ip_cores/wr-cores-local/top/fasec_ref_design/system_top.tcl
+++ b/ip_cores/wr-cores-local/top/fasec_ref_design/system_top.tcl
--- a/ip_cores/wr-cores-local/top/readme_platforms.txt
+++ b/ip_cores/wr-cores-local/top/readme_platforms.txt
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/Manifest.py
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/Manifest.py
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/spec_reset_gen.vhd
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/spec_reset_gen.vhd
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/spec_top.ucf
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/spec_top.ucf
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/spec_top.vhd
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_core_demo/spec_top.vhd
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/Manifest.py
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/Manifest.py
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/spec_top.ucf
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/spec_top.ucf
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/spec_top.vhd
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/spec_top.vhd
--- a/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/timestamp_adder.vhd
+++ b/ip_cores/wr-cores-local/top/spec_1_1/wr_streamers_demo/timestamp_adder.vhd
--- a/ip_cores/wr-cores-local/top/spec_ref_design/Manifest.py
+++ b/ip_cores/wr-cores-local/top/spec_ref_design/Manifest.py
--- a/ip_cores/wr-cores-local/top/spec_ref_design/spec_wr_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/spec_ref_design/spec_wr_ref_top.vhd
--- a/ip_cores/wr-cores-local/top/svec_ref_design/Manifest.py
+++ b/ip_cores/wr-cores-local/top/svec_ref_design/Manifest.py
--- a/ip_cores/wr-cores-local/top/svec_ref_design/svec_wr_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/svec_ref_design/svec_wr_ref_top.vhd
--- a/ip_cores/wr-cores-local/top/vfchd_ref_design/Manifest.py
+++ b/ip_cores/wr-cores-local/top/vfchd_ref_design/Manifest.py
--- a/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
+++ b/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
--- a/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
+++ b/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
--- a/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/README
+++ b/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/README
--- a/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
+++ b/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
--- a/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
+++ b/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
--- a/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
--- a/ip_cores/wr-cores-local/top/vxs_ref_design/Manifest.py
+++ b/ip_cores/wr-cores-local/top/vxs_ref_design/Manifest.py
--- a/ip_cores/wr-cores-local/top/vxs_ref_design/vxs_wr_ref_top.ucf
+++ b/ip_cores/wr-cores-local/top/vxs_ref_design/vxs_wr_ref_top.ucf
--- a/ip_cores/wr-cores-local/top/vxs_ref_design/vxs_wr_ref_top.vhd
+++ b/ip_cores/wr-cores-local/top/vxs_ref_design/vxs_wr_ref_top.vhd
--- a/modules/obsolete_modules/wrsw_swcore/new_allocator/swc_multiport_page_allocator.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/new_allocator/swc_multiport_page_allocator.vhd
--- a/modules/obsolete_modules/wrsw_swcore/new_allocator/swc_page_alloc.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/new_allocator/swc_page_alloc.vhd
--- a/modules/obsolete_modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd
--- a/modules/obsolete_modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
--- a/modules/obsolete_modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
--- a/modules/obsolete_modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc.vhd
--- a/modules/obsolete_modules/wrsw_swcore/swc_multiport_lost_pck_dealloc.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/swc_multiport_lost_pck_dealloc.vhd
--- a/modules/obsolete_modules/wrsw_swcore/xswc_output_block.vhd
+++ b/modules/obsolete_modules/wrsw_swcore/xswc_output_block.vhd
--- a/modules/wrsw_hwiu/Manifest.py
+++ b/modules/wrsw_hwiu/Manifest.py
--- a/modules/wrsw_hwiu/gen_ver.py
+++ b/modules/wrsw_hwiu/gen_ver.py
--- a/modules/wrsw_hwiu/gw_ver_pkg.vhd
+++ b/modules/wrsw_hwiu/gw_ver_pkg.vhd
--- a/modules/wrsw_hwiu/hwinfo_pkg.vhd
+++ b/modules/wrsw_hwiu/hwinfo_pkg.vhd
--- a/modules/wrsw_hwiu/hwiu_wbgen2_pkg.vhd
+++ b/modules/wrsw_hwiu/hwiu_wbgen2_pkg.vhd
--- a/modules/wrsw_hwiu/hwiu_wishbone_slave.vhd
+++ b/modules/wrsw_hwiu/hwiu_wishbone_slave.vhd
--- a/modules/wrsw_hwiu/wrsw_hwiu.vhd
+++ b/modules/wrsw_hwiu/wrsw_hwiu.vhd
--- a/modules/wrsw_hwiu/wrsw_hwiu.wb
+++ b/modules/wrsw_hwiu/wrsw_hwiu.wb
--- a/modules/wrsw_hwiu/xwrsw_hwiu.vhd
+++ b/modules/wrsw_hwiu/xwrsw_hwiu.vhd
--- a/modules/wrsw_pstats/Manifest.py
+++ b/modules/wrsw_pstats/Manifest.py
--- a/modules/wrsw_pstats/irq_ram.vhd
+++ b/modules/wrsw_pstats/irq_ram.vhd
--- a/modules/wrsw_pstats/port_cntr.vhd
+++ b/modules/wrsw_pstats/port_cntr.vhd
--- a/modules/wrsw_pstats/pstats_wbgen2_pkg.vhd
+++ b/modules/wrsw_pstats/pstats_wbgen2_pkg.vhd
--- a/modules/wrsw_pstats/pstats_wishbone_slave.vhd
+++ b/modules/wrsw_pstats/pstats_wishbone_slave.vhd
--- a/modules/wrsw_pstats/wrsw_dummy/Manifest.py
+++ b/modules/wrsw_pstats/wrsw_dummy/Manifest.py
--- a/modules/wrsw_pstats/wrsw_dummy/dummy_regs.h
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_regs.h
--- a/modules/wrsw_pstats/wrsw_dummy/dummy_rmon.vhd
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_rmon.vhd
--- a/modules/wrsw_pstats/wrsw_dummy/dummy_wbgen2_pkg.vhd
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_wbgen2_pkg.vhd
--- a/modules/wrsw_pstats/wrsw_dummy/dummy_wishbone_slave.vhd
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_wishbone_slave.vhd
--- a/modules/wrsw_pstats/wrsw_dummy/wrsw_dummy.wb
+++ b/modules/wrsw_pstats/wrsw_dummy/wrsw_dummy.wb
--- a/modules/wrsw_pstats/wrsw_pstats.vhd
+++ b/modules/wrsw_pstats/wrsw_pstats.vhd
--- a/modules/wrsw_pstats/wrsw_pstats.wb
+++ b/modules/wrsw_pstats/wrsw_pstats.wb
--- a/modules/wrsw_pstats/xwrsw_pstats.vhd
+++ b/modules/wrsw_pstats/xwrsw_pstats.vhd
--- a/modules/wrsw_psu/Manifest.py
+++ b/modules/wrsw_psu/Manifest.py
--- a/modules/wrsw_psu/psu_announce_snooper.vhd
+++ b/modules/wrsw_psu/psu_announce_snooper.vhd
--- a/modules/wrsw_psu/psu_packet_injection.vhd
+++ b/modules/wrsw_psu/psu_packet_injection.vhd
--- a/modules/wrsw_psu/psu_pkg.vhd
+++ b/modules/wrsw_psu/psu_pkg.vhd
--- a/modules/wrsw_psu/psu_tx_ctrl.vhd
+++ b/modules/wrsw_psu/psu_tx_ctrl.vhd
--- a/modules/wrsw_psu/psu_wbgen2_pkg.vhd
+++ b/modules/wrsw_psu/psu_wbgen2_pkg.vhd
--- a/modules/wrsw_psu/psu_wishbone_controller.vhd
+++ b/modules/wrsw_psu/psu_wishbone_controller.vhd
--- a/modules/wrsw_psu/psu_wishbone_controller.wb
+++ b/modules/wrsw_psu/psu_wishbone_controller.wb
--- a/modules/wrsw_psu/xwrsw_psu.vhd
+++ b/modules/wrsw_psu/xwrsw_psu.vhd
--- a/modules/wrsw_rt_subsystem/Manifest.py
+++ b/modules/wrsw_rt_subsystem/Manifest.py
--- a/modules/wrsw_rt_subsystem/gen10_wbgen2_pkg.vhd
+++ b/modules/wrsw_rt_subsystem/gen10_wbgen2_pkg.vhd
--- a/modules/wrsw_rt_subsystem/gen10_wishbone_slave.vhd
+++ b/modules/wrsw_rt_subsystem/gen10_wishbone_slave.vhd
--- a/modules/wrsw_rt_subsystem/wrsw_gen_10mhz.wb
+++ b/modules/wrsw_rt_subsystem/wrsw_gen_10mhz.wb
--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
--- a/modules/wrsw_rt_subsystem/xwrsw_gen_10mhz.vhd
+++ b/modules/wrsw_rt_subsystem/xwrsw_gen_10mhz.vhd
--- a/modules/wrsw_rtu/Manifest.py
+++ b/modules/wrsw_rtu/Manifest.py
--- a/modules/wrsw_rtu/PCK_CRC16_D16.vhd
+++ b/modules/wrsw_rtu/PCK_CRC16_D16.vhd
--- a/modules/wrsw_rtu/pack_unpack_pkg.vhd
+++ b/modules/wrsw_rtu/pack_unpack_pkg.vhd
--- a/modules/wrsw_rtu/rtu_components_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_components_pkg.vhd
--- a/modules/wrsw_rtu/rtu_crc.vhd
+++ b/modules/wrsw_rtu/rtu_crc.vhd
--- a/modules/wrsw_rtu/rtu_crc_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_crc_pkg.vhd
--- a/modules/wrsw_rtu/rtu_fast_match.vhd
+++ b/modules/wrsw_rtu/rtu_fast_match.vhd
--- a/modules/wrsw_rtu/rtu_lookup_engine.vhd
+++ b/modules/wrsw_rtu/rtu_lookup_engine.vhd
--- a/modules/wrsw_rtu/rtu_match.vhd
+++ b/modules/wrsw_rtu/rtu_match.vhd
--- a/modules/wrsw_rtu/rtu_port.vhd
+++ b/modules/wrsw_rtu/rtu_port.vhd
--- a/modules/wrsw_rtu/rtu_port_new.vhd
+++ b/modules/wrsw_rtu/rtu_port_new.vhd
--- a/modules/wrsw_rtu/rtu_private_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_private_pkg.vhd
--- a/modules/wrsw_rtu/rtu_rr_arbiter.vhd
+++ b/modules/wrsw_rtu/rtu_rr_arbiter.vhd
--- a/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
--- a/modules/wrsw_rtu/rtu_wishbone_slave.vhd
+++ b/modules/wrsw_rtu/rtu_wishbone_slave.vhd
--- a/modules/wrsw_rtu/rtu_wishbone_slave.wb
+++ b/modules/wrsw_rtu/rtu_wishbone_slave.wb
--- a/modules/wrsw_rtu/rtu_wishbone_slave_new.wb
+++ b/modules/wrsw_rtu/rtu_wishbone_slave_new.wb
--- a/modules/wrsw_rtu/wrsw_rtu.vhd
+++ b/modules/wrsw_rtu/wrsw_rtu.vhd
--- a/modules/wrsw_rtu/xwrsw_rtu.vhd
+++ b/modules/wrsw_rtu/xwrsw_rtu.vhd
--- a/modules/wrsw_rtu/xwrsw_rtu_new.vhd
+++ b/modules/wrsw_rtu/xwrsw_rtu_new.vhd
--- a/modules/wrsw_shared_types_pkg.vhd
+++ b/modules/wrsw_shared_types_pkg.vhd
--- a/modules/wrsw_swcore/.gitignore
+++ b/modules/wrsw_swcore/.gitignore
--- a/modules/wrsw_swcore/Manifest.py
+++ b/modules/wrsw_swcore/Manifest.py
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/LICENSE
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/LICENSE
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/Manifest.py
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/Manifest.py
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/README
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/README
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/README.md
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/README.md
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/dpram.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/dpram.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/dpram_bbs.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/dpram_bbs.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_1ht.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_1ht.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_bin.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_bin.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_reg.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_reg.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_lvt.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_lvt.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_reg.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_reg.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_xor.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_xor.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/mrram.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/mrram.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/mrram_swt.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/mrram_swt.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/smpram.sdc
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/smpram.sdc
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/smpram.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/smpram.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/smpram_tb.v
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/smpram_tb.v
--- a/modules/wrsw_swcore/Switched-Multiported-RAM/utils.vh
+++ b/modules/wrsw_swcore/Switched-Multiported-RAM/utils.vh
--- a/modules/wrsw_swcore/TODOlist
+++ b/modules/wrsw_swcore/TODOlist
--- a/modules/wrsw_swcore/mpm/Manifest.py
+++ b/modules/wrsw_swcore/mpm/Manifest.py
--- a/modules/wrsw_swcore/mpm/mpm_async_fifo.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_async_fifo.vhd
--- a/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
--- a/modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd
--- a/modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd
--- a/modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd
--- a/modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd
--- a/modules/wrsw_swcore/mpm/mpm_pkg.vhd
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--- a/modules/wrsw_swcore/mpm/mpm_private_pkg.vhd
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--- a/modules/wrsw_swcore/mpm/mpm_read_path.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_read_path.vhd
--- a/modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd
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--- a/modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
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--- a/modules/wrsw_swcore/mpm/mpm_top.vhd
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--- a/modules/wrsw_swcore/mpm/mpm_write_path.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_write_path.vhd
--- a/modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd
+++ b/modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd
--- a/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd
+++ b/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd
--- a/modules/wrsw_swcore/ram_bug/buggy_ram.ngc
+++ b/modules/wrsw_swcore/ram_bug/buggy_ram.ngc
--- a/modules/wrsw_swcore/ram_bug/buggy_ram_synth.vhd
+++ b/modules/wrsw_swcore/ram_bug/buggy_ram_synth.vhd
--- a/modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd
+++ b/modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd
--- a/modules/wrsw_swcore/swc_alloc_resource_manager.vhd
+++ b/modules/wrsw_swcore/swc_alloc_resource_manager.vhd
--- a/modules/wrsw_swcore/swc_core.vhd
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--- a/modules/wrsw_swcore/swc_ll_read_data_validation.vhd
+++ b/modules/wrsw_swcore/swc_ll_read_data_validation.vhd
--- a/modules/wrsw_swcore/swc_multiport_linked_list.vhd
+++ b/modules/wrsw_swcore/swc_multiport_linked_list.vhd
--- a/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
+++ b/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
--- a/modules/wrsw_swcore/swc_ob_prio_queue.vhd
+++ b/modules/wrsw_swcore/swc_ob_prio_queue.vhd
--- a/modules/wrsw_swcore/swc_output_queue_scheduler.vhd
+++ b/modules/wrsw_swcore/swc_output_queue_scheduler.vhd
--- a/modules/wrsw_swcore/swc_output_traffic_shaper.vhd
+++ b/modules/wrsw_swcore/swc_output_traffic_shaper.vhd
--- a/modules/wrsw_swcore/swc_pck_pg_free_module.vhd
+++ b/modules/wrsw_swcore/swc_pck_pg_free_module.vhd
--- a/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
+++ b/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
--- a/modules/wrsw_swcore/swc_pck_transfer_input.vhd
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--- a/modules/wrsw_swcore/swc_pck_transfer_output.vhd
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--- a/modules/wrsw_swcore/swc_prio_encoder.vhd
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--- a/modules/wrsw_swcore/swc_rr_arbiter.vhd
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--- a/modules/wrsw_swcore/swc_swcore_pkg.vhd
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--- a/modules/wrsw_swcore/swc_wbgen2_pkg.vhd
+++ b/modules/wrsw_swcore/swc_wbgen2_pkg.vhd
--- a/modules/wrsw_swcore/swc_wishbone_slave.vhd
+++ b/modules/wrsw_swcore/swc_wishbone_slave.vhd
--- a/modules/wrsw_swcore/wrsw_swcore.wb
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--- a/modules/wrsw_swcore/xswc_core.vhd
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--- a/modules/wrsw_swcore/xswc_input_block.vhd
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--- a/modules/wrsw_swcore/xswc_output_block_new.vhd
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--- a/modules/wrsw_tatsu/Manifest.py
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--- a/modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd
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--- a/modules/wrsw_tatsu/tatsu_wishbone_controller.vhd
+++ b/modules/wrsw_tatsu/tatsu_wishbone_controller.vhd
--- a/modules/wrsw_tatsu/tatsu_wishbone_controller.wb
+++ b/modules/wrsw_tatsu/tatsu_wishbone_controller.wb
--- a/modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd
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--- a/modules/wrsw_tatsu/xwrsw_tatsu.vhd
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--- a/modules/wrsw_tru/Manifest.py
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--- a/modules/wrsw_tru/tru_endpoint.vhd
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--- a/modules/wrsw_tru/tru_port.vhd
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--- a/modules/wrsw_tru/tru_port_wrapper.vhd
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--- a/modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd
+++ b/modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd
--- a/modules/wrsw_tru/tru_sub_vlan_pattern.vhd
+++ b/modules/wrsw_tru/tru_sub_vlan_pattern.vhd
--- a/modules/wrsw_tru/tru_trans_lacp_colect.vhd
+++ b/modules/wrsw_tru/tru_trans_lacp_colect.vhd
--- a/modules/wrsw_tru/tru_trans_lacp_dist.vhd
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--- a/modules/wrsw_tru/tru_trans_marker_trig.vhd
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--- a/modules/wrsw_tru/tru_transition.vhd
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--- a/modules/wrsw_tru/tru_wbgen2_pkg.vhd
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--- a/modules/wrsw_tru/tru_wishbone_slave.html
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--- a/modules/wrsw_tru/tru_wishbone_slave.v
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--- a/modules/wrsw_tru/tru_wishbone_slave.vhd
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--- a/modules/wrsw_tru/tru_wishbone_slave.wb
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--- a/modules/wrsw_tru/wrsw_tru.vhd
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--- a/modules/wrsw_tru/wrsw_tru_pkg.vhd
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--- a/modules/wrsw_tru/wrsw_tru_wb.vhd
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--- a/modules/wrsw_tru/xwrsw_tru.vhd
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--- a/modules/wrsw_watchdog/Manifest.py
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--- a/modules/wrsw_watchdog/build_wb.sh
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--- a/modules/wrsw_watchdog/wdog_wbgen2_pkg.vhd
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--- a/modules/wrsw_watchdog/wdog_wishbone_slave.vhd
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--- a/modules/wrsw_watchdog/wrsw_watchdog.wb
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--- a/modules/wrsw_watchdog/xwrsw_watchdog.vhd
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--- a/platform/altera/.gitignore
+++ b/platform/altera/.gitignore
--- a/platform/altera/Makefile
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--- a/platform/altera/Manifest.py
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--- a/platform/altera/alt_clock_divider.vhd
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--- a/platform/altera/generic_clock_mux3.vhd
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--- a/platform/altera/generic_pipelined_multiplier.vhd
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--- a/platform/altera/generic_ssram_dualport_singleclock.vhd
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--- a/platform/altera/platform_specific.vhd
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--- a/platform/virtex6/chipscope/Manifest.py
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--- a/platform/virtex6/chipscope/chipscope_icon.ngc
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--- a/platform/virtex6/chipscope/chipscope_ila.ngc
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--- a/platform/xilinx/Manifest.py
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--- a/platform/xilinx/ext_pll_100_to_62m.vhd
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--- a/platform/xilinx/ext_pll_10_to_100.vhd
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--- a/platform/xilinx/oserdes_8_to_1.vhd
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--- a/platform/xilinx/pll200MhZ.vhd
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--- a/platform/xilinx/pll_62_5_500mhz.vhd
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--- a/sim/.gitignore
+++ b/sim/.gitignore
--- a/sim/pstats_gen.sv
+++ b/sim/pstats_gen.sv
--- a/sim/regs/hwdu_regs.v
+++ b/sim/regs/hwdu_regs.v
--- a/sim/regs/pstats_regs.vh
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--- a/sim/regs/psu_regs.v
+++ b/sim/regs/psu_regs.v
--- a/sim/regs/rtu_regs.vh
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--- a/sim/regs/tatsu_regs.v
+++ b/sim/regs/tatsu_regs.v
--- a/sim/regs/tru_wb_regs.v
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--- a/sim/regs/wdog_regs.vh
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--- a/sim/simdrv_cpu_bus.sv
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--- a/sim/simdrv_hwdu.svh
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--- a/sim/simdrv_psu.svh
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--- a/sim/simdrv_rtu.sv
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--- a/sim/simdrv_tatsu.svh
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--- a/sim/simdrv_wdog.svh
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--- a/sim/simdrv_wr_tru.svh
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--- a/sim/softpll_regs_ng.vh
+++ b/sim/softpll_regs_ng.vh
--- a/sim/txtsu_regs.v
+++ b/sim/txtsu_regs.v
--- a/syn/.gitignore
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--- a/syn/pts_scb/Manifest.py
+++ b/syn/pts_scb/Manifest.py
--- a/syn/pts_scb/cooolgate.en
+++ b/syn/pts_scb/cooolgate.en
--- a/syn/pts_scb/pts_scb.xise
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--- a/syn/scb_15ports/Manifest.py
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--- a/syn/scb_18ports/.gitignore
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--- a/syn/scb_18ports/Manifest.py
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--- a/syn/scb_18ports/test_scb.xise
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--- a/syn/scb_8ports/Manifest.py
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--- a/syn/scb_8ports/test_scb.xise
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--- a/syn/test_tru/test_tru.xise
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--- a/testbench/10mhz_out/Manifest.py
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--- a/testbench/scb_network_top/Manifest.py
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--- a/testbench/scb_network_top/run.do
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--- a/testbench/scb_network_top/scb_top_sim_svwrap.svh
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--- a/testbench/scb_network_top/simdrv_wr_endpoint.svh
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--- a/testbench/scb_top/Manifest.py
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--- a/testbench/scb_top/alloc.svh
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--- a/testbench/scb_top/main.sv
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--- a/testbench/scb_top/run.do
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--- a/testbench/scb_top/scb_snake_sim_svwrap.svh
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--- a/testbench/scb_top/scb_top_sim_svwrap.svh
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--- a/testbench/scb_top/simdrv_wr_endpoint.svh
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--- a/testbench/scb_top/wave.do
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--- a/testbench/scb_top_8p/Manifest.py
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--- a/testbench/scb_top_8p/main.sv
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--- a/testbench/scb_top_8p/run.do
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--- a/testbench/scb_top_8p/scb_top_sim_svwrap.svh
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--- a/testbench/scb_top_8p/simdrv_wr_endpoint.svh
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--- a/testbench/scb_top_8p/wave.do
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--- a/testbench/swc_async/mem/ILinkedList.svh
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--- a/testbench/swc_async/mem/IShadowFBM.svh
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--- a/testbench/swc_async/mem/Manifest.py
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--- a/testbench/swc_async/mem/main.sv
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--- a/testbench/swc_async/mem/mpm_top_svwrap.svh
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--- a/testbench/swc_async/mem/run.do
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--- a/testbench/swcore/.gitignore
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--- a/testbench/swcore/Manifest.py
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--- a/testbench/swcore/README
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--- a/testbench/swcore/allocator/Manifest.py
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--- a/testbench/swcore/allocator/common.svh
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--- a/testbench/swcore/allocator/main.sv
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--- a/testbench/swcore/allocator/multiport.sv
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--- a/testbench/swcore/allocator/run.do
+++ b/testbench/swcore/allocator/run.do
--- a/testbench/swcore/allocator/wave.do
+++ b/testbench/swcore/allocator/wave.do
--- a/testbench/swcore/fabric_demo_tap.sv
+++ b/testbench/swcore/fabric_demo_tap.sv
--- a/testbench/swcore/fabric_emu.sv
+++ b/testbench/swcore/fabric_emu.sv
--- a/testbench/swcore/fabric_emu_defs.sv
+++ b/testbench/swcore/fabric_emu_defs.sv
--- a/testbench/swcore/fabric_emu_demo.sv
+++ b/testbench/swcore/fabric_emu_demo.sv
--- a/testbench/swcore/fabric_emu_funcs.sv
+++ b/testbench/swcore/fabric_emu_funcs.sv
--- a/testbench/swcore/l0_init.mif
+++ b/testbench/swcore/l0_init.mif
--- a/testbench/swcore/optimized_allocator/Manifest.py
+++ b/testbench/swcore/optimized_allocator/Manifest.py
--- a/testbench/swcore/optimized_allocator/common.svh
+++ b/testbench/swcore/optimized_allocator/common.svh
--- a/testbench/swcore/optimized_allocator/main.sv
+++ b/testbench/swcore/optimized_allocator/main.sv
--- a/testbench/swcore/optimized_allocator/multiport.sv
+++ b/testbench/swcore/optimized_allocator/multiport.sv
--- a/testbench/swcore/optimized_allocator/run-multiport.do
+++ b/testbench/swcore/optimized_allocator/run-multiport.do
--- a/testbench/swcore/optimized_allocator/run.do
+++ b/testbench/swcore/optimized_allocator/run.do
--- a/testbench/swcore/run.do
+++ b/testbench/swcore/run.do
--- a/testbench/swcore/sim_core.do
+++ b/testbench/swcore/sim_core.do
--- a/testbench/swcore/sim_core_single_port.do
+++ b/testbench/swcore/sim_core_single_port.do
--- a/testbench/swcore/sim_input_block.do
+++ b/testbench/swcore/sim_input_block.do
--- a/testbench/swcore/sim_multiport_allocator.do
+++ b/testbench/swcore/sim_multiport_allocator.do
--- a/testbench/swcore/sim_multiport_linked_list.do
+++ b/testbench/swcore/sim_multiport_linked_list.do
--- a/testbench/swcore/sim_multiport_lost_pck_dealloc.do
+++ b/testbench/swcore/sim_multiport_lost_pck_dealloc.do
--- a/testbench/swcore/sim_ob_prio_queue.do
+++ b/testbench/swcore/sim_ob_prio_queue.do
--- a/testbench/swcore/sim_output_block.do
+++ b/testbench/swcore/sim_output_block.do
--- a/testbench/swcore/sim_packet_mem.do
+++ b/testbench/swcore/sim_packet_mem.do
--- a/testbench/swcore/sim_page_alloc.do
+++ b/testbench/swcore/sim_page_alloc.do
--- a/testbench/swcore/sim_pck_transfer_arbiter.do
+++ b/testbench/swcore/sim_pck_transfer_arbiter.do
--- a/testbench/swcore/sim_pck_transfer_input.do
+++ b/testbench/swcore/sim_pck_transfer_input.do
--- a/testbench/swcore/sim_prio_enc.do
+++ b/testbench/swcore/sim_prio_enc.do
--- a/testbench/swcore/sim_read_pump.do
+++ b/testbench/swcore/sim_read_pump.do
--- a/testbench/swcore/sim_rr_arbiter.do
+++ b/testbench/swcore/sim_rr_arbiter.do
--- a/testbench/swcore/sim_write_pump.do
+++ b/testbench/swcore/sim_write_pump.do
--- a/testbench/swcore/swc_block_alloc.c
+++ b/testbench/swcore/swc_block_alloc.c
--- a/testbench/swcore/swc_core_7ports.sv
+++ b/testbench/swcore/swc_core_7ports.sv
--- a/testbench/swcore/swc_core_generic.sv
+++ b/testbench/swcore/swc_core_generic.sv
--- a/testbench/swcore/swc_core_wrapper_7ports.vhd
+++ b/testbench/swcore/swc_core_wrapper_7ports.vhd
--- a/testbench/swcore/swc_core_wrapper_generic.svh
+++ b/testbench/swcore/swc_core_wrapper_generic.svh
--- a/testbench/swcore/swc_input_block.sv
+++ b/testbench/swcore/swc_input_block.sv
--- a/testbench/swcore/swc_multiport_allocator_tb.v
+++ b/testbench/swcore/swc_multiport_allocator_tb.v
--- a/testbench/swcore/swc_multiport_linked_list_tb.v
+++ b/testbench/swcore/swc_multiport_linked_list_tb.v
--- a/testbench/swcore/swc_multiport_lost_pck_dealloc_tb.v
+++ b/testbench/swcore/swc_multiport_lost_pck_dealloc_tb.v
--- a/testbench/swcore/swc_ob_prio_quque_tb.v
+++ b/testbench/swcore/swc_ob_prio_quque_tb.v
--- a/testbench/swcore/swc_output_block_tb.v
+++ b/testbench/swcore/swc_output_block_tb.v
--- a/testbench/swcore/swc_packet_mem_tb.v
+++ b/testbench/swcore/swc_packet_mem_tb.v
--- a/testbench/swcore/swc_page_alloc_tb.v
+++ b/testbench/swcore/swc_page_alloc_tb.v
--- a/testbench/swcore/swc_param_defs.svh
+++ b/testbench/swcore/swc_param_defs.svh
--- a/testbench/swcore/swc_pck_transfer_arbiter_tb.v
+++ b/testbench/swcore/swc_pck_transfer_arbiter_tb.v
--- a/testbench/swcore/swc_pck_transfer_input_tb.v
+++ b/testbench/swcore/swc_pck_transfer_input_tb.v
--- a/testbench/swcore/swc_prio_encoder_tb.v
+++ b/testbench/swcore/swc_prio_encoder_tb.v
--- a/testbench/swcore/swc_read_pump_tb.sv
+++ b/testbench/swcore/swc_read_pump_tb.sv
--- a/testbench/swcore/swc_read_pump_tb.v
+++ b/testbench/swcore/swc_read_pump_tb.v
--- a/testbench/swcore/swc_rr_arbiter_tb.v
+++ b/testbench/swcore/swc_rr_arbiter_tb.v
--- a/testbench/swcore/swc_write_pump_tb.v
+++ b/testbench/swcore/swc_write_pump_tb.v
--- a/testbench/swcore/wtf.do
+++ b/testbench/swcore/wtf.do
--- a/testbench/swcore/xswc_core_wrapper_7ports.svh
+++ b/testbench/swcore/xswc_core_wrapper_7ports.svh
--- a/testbench/tru/Manifest.py
+++ b/testbench/tru/Manifest.py
--- a/testbench/tru/run.do
+++ b/testbench/tru/run.do
--- a/testbench/tru/simdrv_wr_tru.svh
+++ b/testbench/tru/simdrv_wr_tru.svh
--- a/testbench/tru/tru.sv
+++ b/testbench/tru/tru.sv
--- a/testbench/tru/tru_old.sv
+++ b/testbench/tru/tru_old.sv
--- a/testbench/tru/tru_wb_regs.v
+++ b/testbench/tru/tru_wb_regs.v
--- a/testbench/tru/wave.do
+++ b/testbench/tru/wave.do
--- a/testbench/tru/wrsw_tru_wb.vhd
+++ b/testbench/tru/wrsw_tru_wb.vhd
--- a/testbench/wrsw_pstats/Manifest.py
+++ b/testbench/wrsw_pstats/Manifest.py
--- a/testbench/wrsw_pstats/main.sv
+++ b/testbench/wrsw_pstats/main.sv
--- a/testbench/wrsw_pstats/run.do
+++ b/testbench/wrsw_pstats/run.do
--- a/testbench/wrsw_pstats/wave.do
+++ b/testbench/wrsw_pstats/wave.do
--- a/testbench/wrsw_rt_subsystem/Manifest.py
+++ b/testbench/wrsw_rt_subsystem/Manifest.py
--- a/top/bare_top/Manifest.py
+++ b/top/bare_top/Manifest.py
--- a/top/bare_top/gen_sdbsyn.py
+++ b/top/bare_top/gen_sdbsyn.py
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
--- a/top/bare_top/scb_top_sim.vhd
+++ b/top/bare_top/scb_top_sim.vhd
--- a/top/bare_top/wb_cpu_bridge.vhd
+++ b/top/bare_top/wb_cpu_bridge.vhd
--- a/top/bare_top/wrs_sdb_pkg.vhd
+++ b/top/bare_top/wrs_sdb_pkg.vhd
--- a/top/bare_top/wrsw_components_pkg.vhd
+++ b/top/bare_top/wrsw_components_pkg.vhd
--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
--- a/top/scb_15ports/Manifest.py
+++ b/top/scb_15ports/Manifest.py
--- a/top/scb_15ports/scb_top_synthesis.ucf
+++ b/top/scb_15ports/scb_top_synthesis.ucf
--- a/top/scb_15ports/scb_top_synthesis.vhd
+++ b/top/scb_15ports/scb_top_synthesis.vhd
--- a/top/scb_18ports/Manifest.py
+++ b/top/scb_18ports/Manifest.py
--- a/top/scb_18ports/scb_top_synthesis.ucf
+++ b/top/scb_18ports/scb_top_synthesis.ucf
--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
--- a/top/scb_18ports/scb_top_synthesis.xdc
+++ b/top/scb_18ports/scb_top_synthesis.xdc
--- a/top/scb_18ports/swcore_pll.vhd
+++ b/top/scb_18ports/swcore_pll.vhd
--- a/top/scb_8ports/Manifest.py
+++ b/top/scb_8ports/Manifest.py
--- a/top/scb_8ports/scb_top_synthesis.ucf
+++ b/top/scb_8ports/scb_top_synthesis.ucf
--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
--- a/top/scb_8ports/swcore_pll.vhd
+++ b/top/scb_8ports/swcore_pll.vhd