[PSU] WIP: commiting before starting new idea (with snooper RAM)

081b7af2 · Maciej Lipinski · Marek Gumiński · e722feff · 081b7af2 · 081b7af2
Commit 081b7af2 authored Mar 18, 2015 by Maciej Lipinski Committed by Marek Gumiński Aug 19, 2019
Hide whitespace changes
Inline Side-by-side

Showing with 51 additions and 15 deletions

psu_pkg.vhd modules/wrsw_psu/psu_pkg.vhd +16 -0

xwrsw_psu.vhd modules/wrsw_psu/xwrsw_psu.vhd +35 -15

No files found.
--- a/modules/wrsw_psu/psu_pkg.vhd
+++ b/modules/wrsw_psu/psu_pkg.vhd
@@ -70,6 +70,22 @@ package psu_pkg is
      clock_class_valid_o   : out std_logic;
      ignore_rx_port_id_i   :  in std_logic);
  end component;
+  component psu_packet_injection is
+    port (
+      clk_sys_i : in std_logic;
+      rst_n_i   : in std_logic;
+      src_i : in  t_wrf_source_in;
+      src_o : out t_wrf_source_out;
+      snk_i : in  t_wrf_sink_in;
+      snk_o : out t_wrf_sink_out;
+      inject_req_i        : in  std_logic;
+      inject_ready_o      : out std_logic;
+      inject_packet_sel_i : in  std_logic_vector(2 downto 0);
+      inject_user_value_i : in  std_logic_vector(15 downto 0);
+      inject_mode_i       : in  std_logic_vector(1 downto 0);
+      mem_addr_o : out std_logic_vector(9 downto 0);
+      mem_data_i : in  std_logic_vector(17 downto 0));
+  end component;

 end psu_pkg;


--- a/modules/wrsw_psu/xwrsw_psu.vhd
+++ b/modules/wrsw_psu/xwrsw_psu.vhd
@@ -107,6 +107,9 @@ architecture behavioral of xwrsw_psu is
    signal tx_ram_addr            : std_logic_vector( 7 downto 0);
    signal rx_ram_data            : std_logic_vector(15 downto 0);
    signal tx_ram_data            : std_logic_vector(15 downto 0);
+    
+    signal mem_addr               : std_logic_vector(9 downto 0);
+    signal mem_data               : std_logic_vector(17 downto 0)
 begin

  tx_snooper: psu_announce_snooper
@@ -147,21 +150,38 @@ begin
      clock_class_valid_o   => rx_clock_class_valid,
      ignore_rx_port_id_i   => '1');

--   RXTX_RAM : generic_dpram
--     generic map (
--       g_data_width => 16,
--       g_size       => 256,
--       g_dual_clock => false)
--     port map (
--       rst_n_i => rst_n_i,
--       clka_i  => clk_sys_i,
--       clkb_i  => '0',
--       wea_i   => '0',
--       aa_i    => ,
--       qa_o    => ,
--       web_i   => ,
--       ab_i    => ,
--       db_i    => );
+
+  tx_pck_injector: psu_packet_injection
+    port map(
+      clk_sys_i             => clk_sys_i,
+      rst_n_i               => rst_n_i,
+      src_i                 => tx_src_i,
+      src_o                 => tx_src_o,
+      snk_i                 => tx_snk_i,
+      snk_o                 => tx_snk_o,
+      inject_req_i          => ,
+      inject_ready_o        => ,
+      inject_packet_sel_i   => ,
+      inject_user_value_i   => ,
+      inject_mode_i         => ,
+      mem_addr_o            => mem_addr,
+      mem_data_i            => mem_data);
+
+  RXTX_RAM : generic_dpram
+    generic map (
+      g_data_width          => 18,
+      g_size                => 512,
+      g_dual_clock          => false)
+    port map (
+      rst_n_i               => rst_n_i,
+      clka_i                => clk_sys_i,
+      clkb_i                => '0',
+      wea_i                 => '0',
+      aa_i                  => mem_addr,
+      qa_o                  => mem_data,
+      web_i                 => ,
+      ab_i                  => ,
+      db_i                  => );


    tx_src_o            <= tx_snk_i;