This follows update of the top in: top/spec_1_1/wr_streamers_demo
that is used by this testbench. After the updated of the top, few
changes were needed in the simulation:
- update of inputs/outputs in the main
- addition of a (dummy) synthesis_description.vhd (this is generated
  when synthesising, yet needed for compilation in simulation. Since,
  the data in this file is not really important in simulation, no
  need for generation of the file, dummy version is OK
- waveform updated

The streamers demo was using very old top. With the updated of resets,
etc, it stopped working (at least the testbench did stop). So, I finally
updated this top to work (in the testbench at least) with the new BSP.
This required a major re-do of the top. I left from the old as much
as I could. The new top is based on the spec_ref_design. This was
tested only for simulation
(testbech/wr_streamers/streamers-on-spec_trigger-distribution).
A commit with updates to simulation follows.

hdl: introduce "g_verbose" generic to control the printing of information messages during simulation.

This affects in particular the messages about loading of LM32 software, as well as the messages printed by the wishbone crossbar, listing all attached slaves.

If omitted, the default value is "TRUE", in order to maintain backward compatibility.

GTP reference clock is connected to CLK01 and/or CLK11 in our instance of GTP_DUAL.

According to UG386, figure 2-3, page 41, REFSELDYPLLx must be set to '4' to select
CLK10/CLK11.

This is done in order to ensure backward compatibility with previous versions of
the Xilinx platform support package.

Otherwise, counter gets crazy when watchdog resets the swcore and feeds all the
endpoints and NIC with ack=1.

This way one Tx OOB word may be lost, and tx timestamp won't be generated
causing _wrn_start_xmit: descriptor overflow: tx timestamp pending_ message from
wr-nic driver