Commit acd8e81c authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: introduce "g_verbose" generic to control the printing of information…

hdl: introduce "g_verbose" generic to control the printing of information messages during simulation.

This affects in particular the messages about loading of LM32 software, as well as the messages printed by the wishbone crossbar, listing all attached slaves.

If omitted, the default value is "TRUE", in order to maintain backward compatibility.
parent 10772350
......@@ -88,12 +88,14 @@ package wr_board_pkg is
function f_find_default_lm32_firmware (
dpram_initf : string;
simulation : integer;
pcs_16_bit : boolean)
pcs_16_bit : boolean;
verbose : boolean := TRUE)
return string;
component xwrc_board_common is
generic (
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for M25P128
......@@ -319,7 +321,8 @@ package body wr_board_pkg is
function f_find_default_lm32_firmware (
dpram_initf : string;
simulation : integer;
pcs_16_bit : boolean)
pcs_16_bit : boolean;
verbose : boolean := TRUE)
return string is
begin
if((dpram_initf = "default_altera" or dpram_initf = "default_xilinx") and
......@@ -329,28 +332,38 @@ package body wr_board_pkg is
"pcs_16_bit." severity FAILURE;
return "";
elsif (dpram_initf /= "default_altera" and dpram_initf /= "default_xilinx") then
report "[Board:Software for LM32 in WR Core] Using user-provided LM32 " &
"firmware ("&dpram_initf&")." severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using user-provided LM32 " &
"firmware ("&dpram_initf&")." severity NOTE;
end if;
return dpram_initf;
elsif (simulation = 0 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
dpram_initf_default_altera_phy8 /= "") then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8)." severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8)." severity NOTE;
end if;
return dpram_initf_default_altera_phy8;
elsif (simulation = 0 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
dpram_initf_default_xilinx_phy8 /= "") then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilnix, phy8)" severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilnix, phy8)" severity NOTE;
end if;
return dpram_initf_default_xilinx_phy8;
elsif (simulation = 1 and dpram_initf = "default_altera" and pcs_16_bit = FALSE and
dpram_initf_default_altera_phy8_sim /= "") then
report "Board:[Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8, sim)." severity NOTE;
if verbose = TRUE then
report "Board:[Software for LM32 in WR Core] Using release LM32 firmware " &
"(altera, phy8, sim)." severity NOTE;
end if;
return dpram_initf_default_altera_phy8_sim;
elsif (simulation = 1 and dpram_initf = "default_xilinx" and pcs_16_bit = FALSE and
dpram_initf_default_xilinx_phy8_sim /= "") then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilinx, phy8, sim)." severity NOTE;
if verbose = TRUE then
report "[Board:Software for LM32 in WR Core] Using release LM32 firmware " &
"(xilinx, phy8, sim)." severity NOTE;
end if;
return dpram_initf_default_xilinx_phy8_sim;
else
assert FALSE
......
......@@ -49,6 +49,7 @@ use work.wr_board_pkg.all;
entity xwrc_board_common is
generic(
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for M25P128
......@@ -364,6 +365,7 @@ begin -- architecture struct
cmp_xwr_core : xwr_core
generic map (
g_simulation => g_simulation,
g_verbose => g_verbose,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => g_board_name,
g_flash_secsz_kb => g_flash_secsz_kb,
......@@ -373,7 +375,7 @@ begin -- architecture struct
g_aux_clks => g_aux_clks,
g_ep_rxbuf_size => g_ep_rxbuf_size,
g_tx_runt_padding => g_tx_runt_padding,
g_dpram_initf => f_find_default_lm32_firmware(g_dpram_initf, g_simulation, g_pcs_16bit),
g_dpram_initf => f_find_default_lm32_firmware(g_dpram_initf, g_simulation, g_pcs_16bit, FALSE),
g_dpram_size => g_dpram_size,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-07-25
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
......@@ -49,6 +49,7 @@ package wr_spec_pkg is
component xwrc_board_spec is
generic (
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
......@@ -159,6 +160,7 @@ package wr_spec_pkg is
component wrc_board_spec is
generic (
g_simulation : integer := 0;
g_verbose : integer := 1;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "PLAINFBRC";
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-03-20
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -57,6 +57,8 @@ entity wrc_board_spec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to 0 to reduce information messages during simulation
g_verbose : integer := 1;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- Number of aux clocks syntonized by WRPC to WR timebase
......@@ -433,6 +435,7 @@ begin -- architecture struct
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => g_simulation,
g_verbose => f_int2bool(g_verbose),
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-07-25
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -57,6 +57,8 @@ entity xwrc_board_spec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to false to reduce information messages during simulation
g_verbose : boolean := TRUE;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
......@@ -428,6 +430,7 @@ begin -- architecture struct
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_verbose => g_verbose,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SPEC",
g_flash_secsz_kb => 64, -- sector size for M25P32
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-03-20
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
......@@ -49,6 +49,7 @@ package wr_svec_pkg is
component xwrc_board_svec is
generic (
g_simulation : integer := 0;
g_verbose : boolean := TRUE;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
......@@ -158,6 +159,7 @@ package wr_svec_pkg is
component wrc_board_svec is
generic (
g_simulation : integer := 0;
g_verbose : integer := 1;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-06-22
-- Last update: 2019-02-01
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -56,6 +56,8 @@ entity wrc_board_svec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to 0 to reduce information messages during simulation
g_verbose : integer := 1;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- Number of aux clocks syntonized by WRPC to WR timebase
......@@ -428,6 +430,7 @@ begin -- architecture struct
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_simulation => g_simulation,
g_verbose => f_int2bool(g_verbose),
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-06-22
-- Last update: 2019-04-23
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -57,6 +57,8 @@ entity xwrc_board_svec is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- set to false to reduce information messages during simulation
g_verbose : boolean := TRUE;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
......@@ -433,6 +435,7 @@ begin -- architecture struct
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_verbose => g_verbose,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SVEC",
g_flash_secsz_kb => 256, -- default for M25P128
......
Subproject commit 556e4c16302532ac5cb60150c18add695ea1b337
Subproject commit 0ed0cf1d2d8b21a9d92fea949a1ccaa03d9883a2
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2018-03-19
-- Last update: 2019-02-01
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -74,6 +74,8 @@ entity wr_core is
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--up simulation
g_simulation : integer := 0;
-- set to false to reduce the number of information printed during simulation
g_verbose : boolean := true;
g_with_external_clock_input : boolean := true;
--
g_board_name : string := "NA ";
......@@ -312,14 +314,20 @@ architecture struct of wr_core is
begin
if(g_dpram_initf = "default") then
if(g_simulation /= 0) then
report "[WR Core] Using simulation LM32 firmware." severity note;
if g_verbose then
report "[WR Core] Using simulation LM32 firmware." severity note;
end if;
return "wrc-simulation.ram";
else
report "[WR Core] Using release LM32 firmware." severity note;
if g_verbose then
report "[WR Core] Using release LM32 firmware." severity note;
end if;
return "wrc-release.ram";
end if;
else
report "[WR Core] Using user-provided LM32 firmware." severity note;
if g_verbose then
report "[WR Core] Using user-provided LM32 firmware." severity note;
end if;
return g_dpram_initf;
end if;
end function;
......@@ -956,6 +964,7 @@ begin
-----------------------------------------------------------------------------
WB_CON : xwb_sdb_crossbar
generic map(
g_verbose => g_verbose,
g_num_masters => 3,
g_num_slaves => 2,
g_registered => true,
......@@ -1024,6 +1033,7 @@ begin
-----------------------------------------------------------------------------
WB_SECONDARY_CON : xwb_sdb_crossbar
generic map(
g_verbose => g_verbose,
g_num_masters => 1,
g_num_slaves => 9,
g_registered => true,
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Last update: 2018-03-19
-- Last update: 2019-02-01
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -361,6 +361,7 @@ package wrcore_pkg is
component xwr_core is
generic(
g_simulation : integer := 0;
g_verbose : boolean := true;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
......@@ -502,6 +503,7 @@ package wrcore_pkg is
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--up simulation
g_simulation : integer := 0;
g_verbose : boolean := true;
g_with_external_clock_input : boolean := true;
--
g_board_name : string := "NA ";
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2018-03-08
-- Last update: 2019-02-01
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -73,6 +73,8 @@ entity xwr_core is
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--up simulation
g_simulation : integer := 0;
-- set to false to reduce the number of information printed during simulation
g_verbose : boolean := true;
g_with_external_clock_input : boolean := true;
--
g_board_name : string := "NA ";
......@@ -274,6 +276,7 @@ begin
WRPC : wr_core
generic map(
g_simulation => g_simulation,
g_verbose => g_verbose,
g_board_name => g_board_name,
g_flash_secsz_kb => g_flash_secsz_kb,
g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
......
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