Skip to content

W
White Rabbit core collection
Commit 15403bb0 authored by Maciej Lipinski's avatar Maciej Lipinski
Browse files
Options

[wr_streamers_demo] Updated the streamers demo to work Boards Support Package 

The streamers demo was using very old top. With the updated of resets,
etc, it stopped working (at least the testbench did stop). So, I finally
updated this top to work (in the testbench at least) with the new BSP.
This required a major re-do of the top. I left from the old as much
as I could. The new top is based on the spec_ref_design. This was
tested only for simulation
(testbech/wr_streamers/streamers-on-spec_trigger-distribution).
A commit with updates to simulation follows.
parent 94c94685
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 672 additions and 765 deletions
top/spec_1_1/wr_streamers_demo/Manifest.py
View file @ 15403bb0
files = ["spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd","timestamp_adder.vhd" ]
files = ["spec_top.vhd", "spec_top.ucf", "timestamp_adder.vhd" ]
modules = { "local" : ["../../../", "../../../platform/xilinx/chipscope"] }
\ No newline at end of file
modules = { "local" : ["../../../", "../../../platform/xilinx/chipscope",
"../../../board/spec/"] }
top/spec_1_1/wr_streamers_demo/spec_reset_gen.vhd deleted 100644 → 0
View file @ 94c94685
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
top/spec_1_1/wr_streamers_demo/spec_top.ucf
View file @ 15403bb0
This diff is collapsed.
top/spec_1_1/wr_streamers_demo/spec_top.vhd
View file @ 15403bb0
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment