wr_endpoint/ep_rx_bypass_queue.vhd: replaced Xilinx-specific shift register instance with a generic one

simulation models: moved abstract packet sink/source classes away from WB-specific implementations to eth_packet.svh

wr_endpoint/ep_1000basex_pcs.vhd: de-assert busy flag when there's no link to avoid blocking packet source, added some comments

wr_endpoint/ep_tx_framer.vhd: stall-on-beginning of packet bugfix, OOB type checking bugfix, added programmable inter-packet gap (for testing swcore)

wr_endpoint/ep_rx_status_reg_insert.vhd: fixed wrong status reg value (packets outputted from the EP do not include CRCs)