wr_endpoint/ep_tx_pcs_16bit.vhd: adjusted inter-frame gap and TX threshold

4af8fdf7 · Tomasz Wlostowski · b4d88eb5 · 4af8fdf7
Commit 4af8fdf7 authored Jan 23, 2012 by Tomasz Wlostowski
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ep_tx_pcs_16bit.vhd modules/wr_endpoint/ep_tx_pcs_16bit.vhd +3 -3

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--- a/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+++ b/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT section
 -- Created    : 2009-06-16
-- Last update: 2012-01-18
+-- Last update: 2012-01-23
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
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@@ -216,7 +216,7 @@ begin
      g_with_rd_almost_empty   => true,
      g_with_rd_count          => true,
      g_with_wr_almost_full    => true,
-      g_almost_empty_threshold => 16,
+      g_almost_empty_threshold => 32,
      g_almost_full_threshold  => 56)  -- fixme: make this a generic (or WB register)
    port map (
      rst_n_i           => fifo_clear_n,
@@ -443,7 +443,7 @@ begin
            tx_is_k            <= "11";
            tx_odata_reg       <= c_k23_7 & c_k23_7;
            tx_catch_disparity <= '1';
-            tx_cntr            <= "1000";
+            tx_cntr            <= "0100";
            tx_state           <= TX_COMMA_IDLE;

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