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White Rabbit core collection
Commit 9cb82351 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrcore_v2: simmulation models from wishbonized

parent 664ba341
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Showing with 170 additions and 31 deletions
sim/endpoint_regs.v
View file @ 9cb82351
......@@ -97,5 +97,15 @@
`define EP_DSR_LSTATUS 32'h00000001
`define EP_DSR_LACT_OFFSET 1
`define EP_DSR_LACT 32'h00000002
`define ADDR_EP_DMCR 8'h3c
`define EP_DMCR_EN_OFFSET 0
`define EP_DMCR_EN 32'h00000001
`define EP_DMCR_N_AVG_OFFSET 16
`define EP_DMCR_N_AVG 32'h0fff0000
`define ADDR_EP_DMSR 8'h40
`define EP_DMSR_PS_VAL_OFFSET 0
`define EP_DMSR_PS_VAL 32'h00ffffff
`define EP_DMSR_PS_RDY_OFFSET 24
`define EP_DMSR_PS_RDY 32'h01000000
`define BASE_EP_RMON_RAM 8'h80
`define SIZE_EP_RMON_RAM 32'h20
sim/eth_packet.svh
View file @ 9cb82351
......@@ -253,6 +253,7 @@ class EthPacketGenerator;
static const int PCP = (1<<4);
static const int PAYLOAD = (1<<5);
static const int SEQ_PAYLOAD = (1<<7);
static const int SEQ_ID = (1<<10);
static const int TX_OOB = (1<<6);
static const int EVEN_LENGTH = (1<<8);
static const int RX_OOB = (1<<9);
......@@ -261,7 +262,7 @@ class EthPacketGenerator;
protected int r_flags;
protected int m_current_frame_id;
protected int cur_seq_id;
function new();
r_flags =ALL;
......@@ -269,6 +270,8 @@ class EthPacketGenerator;
max_size = 128;
m_current_frame_id = 0;
template = new;
cur_seq_id = 0;
endfunction // new
task set_randomization(int flags);
......@@ -291,6 +294,17 @@ class EthPacketGenerator;
return v;
endfunction // random_bvec
task set_seed(int seed_);
seed = seed_;
endtask // set_seed
function int get_seed();
return seed;
endfunction // get_seed
protected function dyn_array seq_payload(int size);
byte v[];
......@@ -335,6 +349,15 @@ class EthPacketGenerator;
else if(r_flags & SEQ_PAYLOAD) pkt.payload = seq_payload(len);
else pkt.payload = template.payload;
if(r_flags & SEQ_ID)
begin
pkt.payload[0] = cur_seq_id & 'hff;
pkt.payload[1] = (cur_seq_id>>8) & 'hff;
pkt.payload[2] = (cur_seq_id>>16) & 'hff;
pkt.payload[3] = (cur_seq_id>>24) & 'hff;
cur_seq_id++;
end
if(r_flags & TX_OOB)
begin
pkt.ts.frame_id = m_current_frame_id++;
......
sim/if_wb_master.svh
View file @ 9cb82351
......@@ -8,6 +8,11 @@
//
/* Todo:
pipelined reads
settings wrapped in the accessor object
*/
`include "simdrv_defs.svh"
`include "if_wishbone_types.svh"
`include "if_wishbone_accessor.svh"
......@@ -42,8 +47,9 @@ interface IWishboneMaster
int gen_random_throttling;
real throttle_prob;
int little_endian;
int cyc_on_stall;
wb_address_granularity_t addr_gran;
} settings;
modport master
(
......@@ -61,13 +67,16 @@ interface IWishboneMaster
);
function automatic logic[g_addr_width-1:0] gen_addr(uint64_t addr, int xfer_size);
case(g_data_width)
8: return addr;
16: return addr >> 1;
32: return addr >> 2;
64: return addr >> 3;
default: $error("IWishbone: invalid WB data bus width [%d bits\n]", g_data_width);
endcase // case (xfer_size)
if(settings.addr_gran == WORD)
case(g_data_width)
8: return addr;
16: return addr >> 1;
32: return addr >> 2;
64: return addr >> 3;
default: $error("IWishbone: invalid WB data bus width [%d bits\n]", g_data_width);
endcase // case (xfer_size)
else
return addr;
endfunction
function automatic logic[63:0] rev_bits(logic [63:0] x, int nbits);
......@@ -189,28 +198,41 @@ interface IWishboneMaster
if (ack)
ack_cnt--;
endtask
task automatic handle_readback(ref wb_xfer_t xf [$], input int read, ref int cur_rdbk);
if(ack && read)
begin
xf[cur_rdbk].d = dat_i;
cur_rdbk++;
end
endtask // handle_readback
task automatic pipelined_write_cycle
task automatic pipelined_cycle
(
wb_xfer_t xfer[],
int n_xfers,
ref wb_xfer_t xfer[$],
input int write,
input int n_xfers,
output wb_cycle_result_t result
);
int i;
int ack_count ;
int failure ;
int cur_rdbk;
ack_count = 0;
failure = 0;
xf_idle = 0;
cur_rdbk = 0;
if($time != last_access_t)
@(posedge clk_i); /* resynchronize, just in case */
while(stall)
while(stall && !settings.cyc_on_stall)
@(posedge clk_i);
cyc <= 1'b1;
......@@ -221,9 +243,9 @@ interface IWishboneMaster
while(i<n_xfers)
begin
count_ack(ack_count);
handle_readback(xfer, !write, cur_rdbk);
if(err) begin
result = R_ERROR;
failure = 1;
......@@ -246,16 +268,25 @@ interface IWishboneMaster
end else begin
adr <= gen_addr(xfer[i].a, xfer[i].size);
stb <= 1'b1;
we <= 1'b1;
sel <= gen_sel(xfer[i].a, xfer[i].size, settings.little_endian);
dat_o <= gen_data(xfer[i].a, xfer[i].d, xfer[i].size, settings.little_endian);
if(write)
begin
we <= 1'b1;
sel <= gen_sel(xfer[i].a, xfer[i].size, settings.little_endian);
dat_o <= gen_data(xfer[i].a, xfer[i].d, xfer[i].size, settings.little_endian);
end else begin
we<=1'b0;
sel <= 'hffffffff;
end
@(posedge clk_i);
stb <= 1'b0;
we <= 1'b0;
if(stall)
begin
stb <= 1'b1;
we <= 1'b1;
if(write)
we <= 1'b1;
while(stall)
begin
......@@ -291,7 +322,8 @@ interface IWishboneMaster
count_ack(ack_count);
handle_readback(xfer, !write, cur_rdbk);
if(stb && !ack)
ack_count++;
else if(!stb && ack)
......@@ -337,7 +369,7 @@ class CIWBMasterAccessor extends CWishboneAccessor;
return (request_queue.size() == 0) && xf_idle;
endfunction // idle
endclass // CIWBMasterAccessor
function CIWBMasterAccessor get_accessor();
CIWBMasterAccessor tmp;
......@@ -360,8 +392,10 @@ endclass // CIWBMasterAccessor
end
initial begin
settings.gen_random_throttling = 1;
settings.gen_random_throttling = 0;
settings.throttle_prob = 0.1;
settings.cyc_on_stall = 0;
settings.addr_gran = WORD;
end
......@@ -382,12 +416,8 @@ endclass // CIWBMasterAccessor
case(c.ctype)
PIPELINED:
begin
if(c.rw) begin
pipelined_write_cycle(c.data, c.data.size(), res);
c.result =res;
c.data = {};
end
pipelined_cycle(c.data, c.rw, c.data.size(), res);
c.result =res;
end
CLASSIC:
begin
......
sim/if_wishbone_types.svh
View file @ 9cb82351
......@@ -25,6 +25,11 @@ typedef enum
PIPELINED = 1
} wb_cycle_type_t;
typedef enum {
WORD = 0,
BYTE = 1
} wb_address_granularity_t;
typedef struct {
uint64_t a;
uint64_t d;
......
sim/minic_regs.vh
View file @ 9cb82351
......@@ -31,6 +31,11 @@
`define MINIC_DBGR_IRQ_CNT 32'h00ffffff
`define MINIC_DBGR_WB_IRQ_VAL_OFFSET 24
`define MINIC_DBGR_WB_IRQ_VAL 32'h01000000
`define ADDR_MINIC_MPROT 6'h1c
`define MINIC_MPROT_LO_OFFSET 0
`define MINIC_MPROT_LO 32'h0000ffff
`define MINIC_MPROT_HI_OFFSET 16
`define MINIC_MPROT_HI 32'hffff0000
`define ADDR_MINIC_EIC_IDR 6'h20
`define MINIC_EIC_IDR_TX_OFFSET 0
`define MINIC_EIC_IDR_TX 32'h00000001
......
sim/pps_gen_regs.v 0 → 100644
View file @ 9cb82351
`define ADDR_PPSG_CR 5'h0
`define PPSG_CR_CNT_RST_OFFSET 0
`define PPSG_CR_CNT_RST 32'h00000001
`define PPSG_CR_CNT_EN_OFFSET 1
`define PPSG_CR_CNT_EN 32'h00000002
`define PPSG_CR_CNT_ADJ_OFFSET 2
`define PPSG_CR_CNT_ADJ 32'h00000004
`define PPSG_CR_CNT_SET_OFFSET 3
`define PPSG_CR_CNT_SET 32'h00000008
`define PPSG_CR_PWIDTH_OFFSET 4
`define PPSG_CR_PWIDTH 32'hfffffff0
`define ADDR_PPSG_CNTR_NSEC 5'h4
`define ADDR_PPSG_CNTR_UTCLO 5'h8
`define ADDR_PPSG_CNTR_UTCHI 5'hc
`define ADDR_PPSG_ADJ_NSEC 5'h10
`define ADDR_PPSG_ADJ_UTCLO 5'h14
`define ADDR_PPSG_ADJ_UTCHI 5'h18
`define ADDR_PPSG_ESCR 5'h1c
`define PPSG_ESCR_SYNC_OFFSET 0
`define PPSG_ESCR_SYNC 32'h00000001
`define PPSG_ESCR_PPS_VALID_OFFSET 1
`define PPSG_ESCR_PPS_VALID 32'h00000002
`define PPSG_ESCR_TM_VALID_OFFSET 2
`define PPSG_ESCR_TM_VALID 32'h00000004
sim/simdrv_defs.svh
View file @ 9cb82351
......@@ -21,9 +21,10 @@ virtual class CBusAccessor;
virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
int res;
uint64_t aa[], da[];
uint64_t aa[1], da[];
da= new[1];
aa[0] = addr;
readm(aa, da, size, res);
data = da[0];
......@@ -33,7 +34,7 @@ virtual class CBusAccessor;
virtual task write(uint64_t addr, uint64_t data, input int size = 4, ref int result = _null);
uint64_t aa[1], da[1];
aa[0] = addr;
da[1] = data;
da[0] = data;
writem(aa, da, size, result);
endtask
......
sim/softpll_regs.v 0 → 100644
View file @ 9cb82351
`define ADDR_SPLL_CSR 6'h0
`define SPLL_CSR_N_REF_OFFSET 0
`define SPLL_CSR_N_REF 32'h0000003f
`define SPLL_CSR_N_OUT_OFFSET 8
`define SPLL_CSR_N_OUT 32'h00000700
`define ADDR_SPLL_OCCR 6'h4
`define SPLL_OCCR_OUT_EN_OFFSET 0
`define SPLL_OCCR_OUT_EN 32'h000000ff
`define SPLL_OCCR_AUX_LOCK_OFFSET 8
`define SPLL_OCCR_AUX_LOCK 32'h0000ff00
`define ADDR_SPLL_RCER 6'h8
`define ADDR_SPLL_PER_HPLL 6'hc
`define ADDR_SPLL_DAC_HPLL 6'h10
`define ADDR_SPLL_DAC_MAIN 6'h14
`define SPLL_DAC_MAIN_VALUE_OFFSET 0
`define SPLL_DAC_MAIN_VALUE 32'h0000ffff
`define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
`define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
`define ADDR_SPLL_DEGLITCH_THR 6'h18
`define ADDR_SPLL_EIC_IDR 6'h20
`define SPLL_EIC_IDR_TAG_OFFSET 0
`define SPLL_EIC_IDR_TAG 32'h00000001
`define ADDR_SPLL_EIC_IER 6'h24
`define SPLL_EIC_IER_TAG_OFFSET 0
`define SPLL_EIC_IER_TAG 32'h00000001
`define ADDR_SPLL_EIC_IMR 6'h28
`define SPLL_EIC_IMR_TAG_OFFSET 0
`define SPLL_EIC_IMR_TAG 32'h00000001
`define ADDR_SPLL_EIC_ISR 6'h2c
`define SPLL_EIC_ISR_TAG_OFFSET 0
`define SPLL_EIC_ISR_TAG 32'h00000001
`define ADDR_SPLL_TRR_R0 6'h30
`define SPLL_TRR_R0_VALUE_OFFSET 0
`define SPLL_TRR_R0_VALUE 32'h00ffffff
`define SPLL_TRR_R0_CHAN_ID_OFFSET 24
`define SPLL_TRR_R0_CHAN_ID 32'h7f000000
`define SPLL_TRR_R0_DISC_OFFSET 31
`define SPLL_TRR_R0_DISC 32'h80000000
`define ADDR_SPLL_TRR_CSR 6'h34
`define SPLL_TRR_CSR_EMPTY_OFFSET 17
`define SPLL_TRR_CSR_EMPTY 32'h00020000
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