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White Rabbit core collection
Commit 7b5a7685 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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merged with wrcore_v2

parents 3d699c4f 2dd3ddf8
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Showing with 3546 additions and 2887 deletions
modules/fabric/wr_fabric_pkg.vhd
View file @ 7b5a7685
......@@ -59,7 +59,11 @@ package wr_fabric_pkg is
function f_marshall_wrf_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
constant c_dummy_src_in : t_wrf_source_in :=
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wrf_sink_in :=
((others=>'X'), (others=>'X'), '0', '0', 'X', (others=>'X'));
end wr_fabric_pkg;
package body wr_fabric_pkg is
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 7b5a7685
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Wed Nov 2 02:18:19 2011
-- Created : Sun Nov 6 00:30:17 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ 7b5a7685
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Wed Nov 2 02:18:19 2011
-- Created : Sun Nov 6 00:30:17 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ 7b5a7685
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2011-11-02
-- Last update: 2012-01-25
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -329,20 +329,15 @@ begin -- behavioral
end process;
mem_arb_tx <= not mem_arb_rx;
mem_addr_int <= std_logic_vector(ntx_mem_a) when mem_arb_rx = '0' else std_logic_vector(nrx_mem_a);
mem_addr_int <= std_logic_vector(ntx_mem_a) when mem_arb_rx = '0' else std_logic_vector(nrx_mem_a);
mem_data_o <= nrx_mem_d;
ntx_mem_d <= mem_data_i;
mem_wr_int <= (nrx_mem_wr and not bad_addr) when mem_arb_rx = '1' else '0';
mem_wr_o <= mem_wr_int;
--mem_wr_int <= (nrx_mem_wr and not bad_addr) when mem_arb_rx = '1' else '0';
--mem_wr_o <= mem_wr_int;
mem_wr_o <= nrx_mem_wr when mem_arb_rx = '1' else '0';
mem_addr_o <= mem_addr_int;
TRIG0(g_memsize_log2-1 downto 0) <= mem_addr_int;
trig0(16) <= bad_addr;
trig0(17) <= nrx_mem_wr;
trig0(18) <= mem_arb_rx;
trig1 <= nrx_mem_d;
trig0(19) <= mem_wr_int;
p_gen_bad_addr : process(mem_addr_int, regs_out)
......@@ -648,6 +643,22 @@ begin -- behavioral
-- RX Path (Fabric -> Host)
-------------------------------------------------------------------------------
--TRIG0(2 downto 0) <= std_logic_vector(nrx_state);
--TRIG0(3) <= nrx_buf_full;
--TRIG0(g_memsize_log2-1+4 downto 4) <= std_logic_vector(nrx_avail);
--TRIG1(g_memsize_log2-1 downto 0) <= mem_addr_int;
--TRIG1(16) <= bad_addr;
--TRIG1(17) <= nrx_mem_wr;
--TRIG1(18) <= mem_arb_rx;
--TRIG2 <= nrx_mem_d;
--TRIG1(19) <= mem_wr_int;
nrx_status_reg <= f_unmarshall_wrf_status(snk_dat_i);
nrx_valid <= '1' when snk_cyc_i = '1' and snk_stall_int = '0' and snk_stb_i = '1' and
......@@ -736,6 +747,7 @@ begin -- behavioral
-- on the RX fabric and then we commence reception of the packet.
-------------------------------------------------------------------------------
when RX_WAIT_SOF =>
-- TRIG0(2 downto 0) <= "000";
nrx_newpacket <= '0';
nrx_done <= '0';
......@@ -762,6 +774,7 @@ begin -- behavioral
-------------------------------------------------------------------------------
when RX_ALLOCATE_DESCRIPTOR =>
-- TRIG0(2 downto 0) <= "001";
-- wait until we have memory access
if(mem_arb_rx = '0') then
......@@ -769,8 +782,10 @@ begin -- behavioral
-- make sure the bit 31 is 0 (RX descriptor is invalid)
nrx_mem_d <= (others => '0');
nrx_mem_a_saved <= nrx_mem_a;
nrx_avail <= nrx_avail - 1;
nrx_mem_wr <= '1';
if(nrx_avail /= to_unsigned(0, nrx_avail'length)) then
nrx_avail <= nrx_avail - 1;
nrx_mem_wr <= '1';
end if;
-- allow the fabric to receive the data
......@@ -784,6 +799,7 @@ begin -- behavioral
-------------------------------------------------------------------------------
when RX_DATA =>
-- TRIG0(2 downto 0) <= "010";
nrx_mem_wr <= '0';
......@@ -805,9 +821,15 @@ begin -- behavioral
end if;
-- abort/error/end-of-frame?
if(nrx_stat_error = '1' or snk_cyc_i = '0') then
nrx_error <= nrx_stat_error;
nrx_done <= '1';
if(nrx_stat_error = '1' or snk_cyc_i = '0' or nrx_avail = to_unsigned(0, nrx_avail'length)) then
if(nrx_stat_error = '1' or nrx_avail = to_unsigned(0, nrx_avail'length)) then
nrx_error <= '1';
else
nrx_error <= '0';
end if;
--nrx_error <= '1' when nrx_stat_error='1' or nrx_avail=to_unsigned(0, nrx_avail'length) else '0';
nrx_done <= '1';
-- flush the remaining packet data into the DMA buffer
nrx_state <= RX_MEM_FLUSH;
......@@ -878,6 +900,7 @@ begin -- behavioral
-------------------------------------------------------------------------------
when RX_MEM_RESYNC =>
-- TRIG0(2 downto 0) <= "011";
-- check for error/abort conditions, they may appear even when
-- the fabric is not accepting the data (tx_dreq_o = 0)
......@@ -898,11 +921,18 @@ begin -- behavioral
-------------------------------------------------------------------------------
when RX_MEM_FLUSH =>
-- TRIG0(2 downto 0) <= "100";
nrx_stall_mask <= '1';
nrx_mem_wr <= '1';
if(nrx_buf_full = '0') then
nrx_mem_wr <= '1';
else
nrx_size <= nrx_size - 1; --the buffer is full, last word was not written
end if;
if(mem_arb_rx = '0') then
nrx_avail <= nrx_avail - 1;
if(nrx_buf_full = '0') then
nrx_avail <= nrx_avail - 1;
end if;
nrx_state <= RX_UPDATE_DESC;
end if;
......@@ -914,6 +944,7 @@ begin -- behavioral
-------------------------------------------------------------------------------
when RX_UPDATE_DESC =>
-- TRIG0(2 downto 0) <= "101";
nrx_stall_mask <= '1';
if(mem_arb_rx = '0') then
......
modules/wrc_core/Manifest.py
View file @ 7b5a7685
files = [ "wr_core.vhd",
files = [ "xwr_core.vhd",
"wr_core.vhd",
"wrc_dpram.vhd",
"wrcore_pkg.vhd",
"wrc_periph.vhd",
"wb_reset.vhd",
"wbp_mux.vhd" ];
modules = {"local" : "wb_conmax"};
"wbp_mux.vhd",
"wrc_syscon_wb.vhd",
"wrc_syscon_pkg.vhd",
"xwr_syscon_wb.vhd"];
modules/wrc_core/build_wb.sh
View file @ 7b5a7685
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrc_syscon.html -p wrc_syscon_pkg.vhd -H record -V wrc_syscon_wb.vhd --cstyle defines --lang vhdl -K ../../sim/wrc_syscon_regs.vh wrc_syscon_wb.wb
wbgen2 -D ./doc/wrc_syscon.html -p wrc_syscon_pkg.vhd -H record -V wrc_syscon_wb.vhd -C wrc_syscon_regs.h --cstyle defines --lang vhdl -K ../../sim/wrc_syscon_regs.vh wrc_syscon_wb.wb
modules/wrc_core/wb_conmax/Manifest.py deleted 100644 → 0
View file @ 3d699c4f
files = ["wb_conmax_pri_dec.vhd", "wb_conmax_pri_enc.vhd", "wb_conmax_arb.vhd", "wb_conmax_msel.vhd",
"wbconmax_pkg.vhd", "wb_conmax_slave_if.vhd", "wb_conmax_master_if.vhd", "wb_conmax_rf.vhd",
"wb_conmax_top.vhd" ];
modules/wrc_core/wb_conmax/wb_conmax_arb.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_arb.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2011-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Simple arbiter with round robin. It does not use any prioritization for
-- WB Masters.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_conmax_arb is
port(
clk_i : in std_logic;
rst_i : in std_logic;
--req_i(n) <- wb_cyc from n-th Master
req_i : in std_logic_vector(7 downto 0);
next_i : in std_logic;
--which master (0 to 7) is granted
gnt_o : out std_logic_vector(2 downto 0)
);
end wb_conmax_arb;
architecture behaviour of wb_conmax_arb is
type t_arb_states is (GRANT0, GRANT1, GRANT2, GRANT3, GRANT4, GRANT5,
GRANT6, GRANT7);
signal s_state : t_arb_states;
begin
--state transitions
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
if(rst_i = '1') then
s_state <= GRANT0;
else
case s_state is
when GRANT0 =>
--if this req is dropped or next is asserted, check for other req's
if(req_i(0)='0' or next_i='1') then
if ( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
end if;
end if;
when GRANT1 =>
if(req_i(1)='0' or next_i='1') then
if ( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
end if;
end if;
when GRANT2 =>
if(req_i(2)='0' or next_i='1') then
if ( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
end if;
end if;
when GRANT3 =>
if(req_i(3)='0' or next_i='1') then
if ( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
end if;
end if;
when GRANT4 =>
if(req_i(4)='0' or next_i='1') then
if ( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
end if;
end if;
when GRANT5 =>
if(req_i(5)='0' or next_i='1') then
if ( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
end if;
end if;
when GRANT6 =>
if(req_i(6)='0' or next_i='1') then
if ( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
end if;
end if;
when GRANT7 =>
if(req_i(7)='0' or next_i='1') then
if ( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
end if;
end if;
when others =>
s_state <= GRANT0;
end case;
end if;
end if;
end process;
process(s_state)
begin
case(s_state) is
when GRANT0 => gnt_o <= "000";
when GRANT1 => gnt_o <= "001";
when GRANT2 => gnt_o <= "010";
when GRANT3 => gnt_o <= "011";
when GRANT4 => gnt_o <= "100";
when GRANT5 => gnt_o <= "101";
when GRANT6 => gnt_o <= "110";
when GRANT7 => gnt_o <= "111";
when others => gnt_o <= "000";
end case;
end process;
end behaviour;
modules/wrc_core/wb_conmax/wb_conmax_master_if.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_master_if.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wishbone interface to connect WB master from outside. Decodes 4 most
-- significant bits of Address bus. Using the selection it multiplexes the
-- Master's WB interface to appropriate Slave interface.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wbconmax_pkg.all;
entity wb_conmax_master_if is
port(
clk_i : in std_logic;
rst_i : in std_logic;
--Master interface
wb_master_i : in t_wb_i;
wb_master_o : out t_wb_o;
--Slaves(0 to 15) interface
wb_slaves_i : in t_conmax_slaves_i;
wb_slaves_o : out t_conmax_slaves_o
);
end wb_conmax_master_if;
architecture behaviour of wb_conmax_master_if is
signal s_slv_sel : std_logic_vector(3 downto 0);
signal s_cyc_o_next : std_logic_vector(15 downto 0);
signal s_cyc_o : std_logic_vector(15 downto 0);
begin
--Select logic
s_slv_sel <= wb_master_i.addr(c_aw-1 downto c_aw-4);
--Address & Data Pass
GEN_OUTS:
for I in 0 to 15 generate
wb_slaves_o(I).addr <= wb_master_i.addr;
wb_slaves_o(I).sel <= wb_master_i.sel;
wb_slaves_o(I).data <= wb_master_i.data;
wb_slaves_o(I).we <= wb_master_i.we;
wb_slaves_o(I).cyc <= s_cyc_o(I);
wb_slaves_o(I).stb <= wb_master_i.stb when(s_slv_sel=std_logic_vector(
to_unsigned(I, 4)) ) else '0';
end generate;
wb_master_o.data <= wb_slaves_i( 0).data when(s_slv_sel="0000") else
wb_slaves_i( 1).data when(s_slv_sel="0001") else
wb_slaves_i( 2).data when(s_slv_sel="0010") else
wb_slaves_i( 3).data when(s_slv_sel="0011") else
wb_slaves_i( 4).data when(s_slv_sel="0100") else
wb_slaves_i( 5).data when(s_slv_sel="0101") else
wb_slaves_i( 6).data when(s_slv_sel="0110") else
wb_slaves_i( 7).data when(s_slv_sel="0111") else
wb_slaves_i( 8).data when(s_slv_sel="1000") else
wb_slaves_i( 9).data when(s_slv_sel="1001") else
wb_slaves_i(10).data when(s_slv_sel="1010") else
wb_slaves_i(11).data when(s_slv_sel="1011") else
wb_slaves_i(12).data when(s_slv_sel="1100") else
wb_slaves_i(13).data when(s_slv_sel="1101") else
wb_slaves_i(14).data when(s_slv_sel="1110") else
wb_slaves_i(15).data when(s_slv_sel="1111") else
(others=>'0');
--Control Signal Pass
G1: for I in 0 to 15 generate
s_cyc_o_next(I) <= s_cyc_o(I) when ( wb_master_i.cyc='1' and wb_master_i.stb='0') else
wb_master_i.cyc when ( s_slv_sel=std_logic_vector(to_unsigned(I, 4)) ) else
'0';
end generate;
process(clk_i)
begin
if( clk_i'event and clk_i='1') then
if(rst_i='1') then
s_cyc_o(15 downto 0) <= (others => '0');
else
s_cyc_o(15 downto 0) <= s_cyc_o_next(15 downto 0);
end if;
end if;
end process;
wb_master_o.ack <= wb_slaves_i( 0).ack when(s_slv_sel="0000") else
wb_slaves_i( 1).ack when(s_slv_sel="0001") else
wb_slaves_i( 2).ack when(s_slv_sel="0010") else
wb_slaves_i( 3).ack when(s_slv_sel="0011") else
wb_slaves_i( 4).ack when(s_slv_sel="0100") else
wb_slaves_i( 5).ack when(s_slv_sel="0101") else
wb_slaves_i( 6).ack when(s_slv_sel="0110") else
wb_slaves_i( 7).ack when(s_slv_sel="0111") else
wb_slaves_i( 8).ack when(s_slv_sel="1000") else
wb_slaves_i( 9).ack when(s_slv_sel="1001") else
wb_slaves_i(10).ack when(s_slv_sel="1010") else
wb_slaves_i(11).ack when(s_slv_sel="1011") else
wb_slaves_i(12).ack when(s_slv_sel="1100") else
wb_slaves_i(13).ack when(s_slv_sel="1101") else
wb_slaves_i(14).ack when(s_slv_sel="1110") else
wb_slaves_i(15).ack when(s_slv_sel="1111") else
'0';
wb_master_o.err <= wb_slaves_i( 0).err when(s_slv_sel="0000") else
wb_slaves_i( 1).err when(s_slv_sel="0001") else
wb_slaves_i( 2).err when(s_slv_sel="0010") else
wb_slaves_i( 3).err when(s_slv_sel="0011") else
wb_slaves_i( 4).err when(s_slv_sel="0100") else
wb_slaves_i( 5).err when(s_slv_sel="0101") else
wb_slaves_i( 6).err when(s_slv_sel="0110") else
wb_slaves_i( 7).err when(s_slv_sel="0111") else
wb_slaves_i( 8).err when(s_slv_sel="1000") else
wb_slaves_i( 9).err when(s_slv_sel="1001") else
wb_slaves_i(10).err when(s_slv_sel="1010") else
wb_slaves_i(11).err when(s_slv_sel="1011") else
wb_slaves_i(12).err when(s_slv_sel="1100") else
wb_slaves_i(13).err when(s_slv_sel="1101") else
wb_slaves_i(14).err when(s_slv_sel="1110") else
wb_slaves_i(15).err when(s_slv_sel="1111") else
'0';
wb_master_o.rty <= wb_slaves_i( 0).rty when(s_slv_sel="0000") else
wb_slaves_i( 1).rty when(s_slv_sel="0001") else
wb_slaves_i( 2).rty when(s_slv_sel="0010") else
wb_slaves_i( 3).rty when(s_slv_sel="0011") else
wb_slaves_i( 4).rty when(s_slv_sel="0100") else
wb_slaves_i( 5).rty when(s_slv_sel="0101") else
wb_slaves_i( 6).rty when(s_slv_sel="0110") else
wb_slaves_i( 7).rty when(s_slv_sel="0111") else
wb_slaves_i( 8).rty when(s_slv_sel="1000") else
wb_slaves_i( 9).rty when(s_slv_sel="1001") else
wb_slaves_i(10).rty when(s_slv_sel="1010") else
wb_slaves_i(11).rty when(s_slv_sel="1011") else
wb_slaves_i(12).rty when(s_slv_sel="1100") else
wb_slaves_i(13).rty when(s_slv_sel="1101") else
wb_slaves_i(14).rty when(s_slv_sel="1110") else
wb_slaves_i(15).rty when(s_slv_sel="1111") else
'0';
end behaviour;
modules/wrc_core/wb_conmax/wb_conmax_msel.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_msel.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Prioritizing arbiter for Slave interface. Uses simple arbitrer
-- (wb_conmax_arb) and takes Master's priorities into account.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_conmax_msel is
generic(
g_pri_sel : integer := 0
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
conf_i : in std_logic_vector(15 downto 0);
req_i : in std_logic_vector(7 downto 0);
next_i : in std_logic;
sel : out std_logic_vector(2 downto 0)
);
end wb_conmax_msel;
architecture behavioral of wb_conmax_msel is
component wb_conmax_pri_enc is
generic(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel : integer := 0
);
port(
valid_i : in std_logic_vector(7 downto 0);
pri0_i : in std_logic_vector(1 downto 0);
pri1_i : in std_logic_vector(1 downto 0);
pri2_i : in std_logic_vector(1 downto 0);
pri3_i : in std_logic_vector(1 downto 0);
pri4_i : in std_logic_vector(1 downto 0);
pri5_i : in std_logic_vector(1 downto 0);
pri6_i : in std_logic_vector(1 downto 0);
pri7_i : in std_logic_vector(1 downto 0);
pri_o : out std_logic_vector(1 downto 0)
);
end component;
component wb_conmax_arb is
port(
clk_i : in std_logic;
rst_i : in std_logic;
req_i : in std_logic_vector(7 downto 0);
gnt_o : out std_logic_vector(2 downto 0);
next_i : in std_logic
);
end component;
signal s_pri0, s_pri1, s_pri2, s_pri3, s_pri4,
s_pri5, s_pri6, s_pri7 : std_logic_vector(1 downto 0);
signal s_pri_out_d, s_pri_out : std_logic_vector(1 downto 0);
signal s_req_p0, s_req_p1, s_req_p2, s_req_p3 : std_logic_vector(7 downto 0);
signal s_gnt_p0, s_gnt_p1, s_gnt_p2, s_gnt_p3 : std_logic_vector(2 downto 0);
signal s_sel1, s_sel2 : std_logic_vector(2 downto 0);
begin
--------------------------------------
--Priority Select logic
G1: if(g_pri_sel=0) generate
s_pri0 <= "00";
s_pri1 <= "00";
s_pri2 <= "00";
s_pri3 <= "00";
s_pri4 <= "00";
s_pri5 <= "00";
s_pri6 <= "00";
s_pri7 <= "00";
end generate;
G2: if(g_pri_sel=2) generate
s_pri0 <= conf_i(1 downto 0);
s_pri1 <= conf_i(3 downto 2);
s_pri2 <= conf_i(5 downto 4);
s_pri3 <= conf_i(7 downto 6);
s_pri4 <= conf_i(9 downto 8);
s_pri5 <= conf_i(11 downto 10);
s_pri6 <= conf_i(13 downto 12);
s_pri7 <= conf_i(15 downto 14);
end generate;
G3: if(g_pri_sel/=0 and g_pri_sel/=2) generate
s_pri0 <= '0' & conf_i(0);
s_pri1 <= '0' & conf_i(2);
s_pri2 <= '0' & conf_i(4);
s_pri3 <= '0' & conf_i(6);
s_pri4 <= '0' & conf_i(8);
s_pri5 <= '0' & conf_i(10);
s_pri6 <= '0' & conf_i(12);
s_pri7 <= '0' & conf_i(14);
end generate;
PRI_ENC: wb_conmax_pri_enc
generic map(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel => g_pri_sel
)
port map(
valid_i => req_i,
pri0_i => s_pri0,
pri1_i => s_pri1,
pri2_i => s_pri2,
pri3_i => s_pri3,
pri4_i => s_pri4,
pri5_i => s_pri5,
pri6_i => s_pri6,
pri7_i => s_pri7,
pri_o => s_pri_out_d
);
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
if(rst_i = '1') then
s_pri_out <= "00";
elsif(next_i = '1') then
s_pri_out <= s_pri_out_d;
end if;
end if;
end process;
-----------------------------------------------
--Arbiters
s_req_p0(0) <= req_i(0) when(s_pri0 = "00") else '0';
s_req_p0(1) <= req_i(1) when(s_pri1 = "00") else '0';
s_req_p0(2) <= req_i(2) when(s_pri2 = "00") else '0';
s_req_p0(3) <= req_i(3) when(s_pri3 = "00") else '0';
s_req_p0(4) <= req_i(4) when(s_pri4 = "00") else '0';
s_req_p0(5) <= req_i(5) when(s_pri5 = "00") else '0';
s_req_p0(6) <= req_i(6) when(s_pri6 = "00") else '0';
s_req_p0(7) <= req_i(7) when(s_pri7 = "00") else '0';
s_req_p1(0) <= req_i(0) when(s_pri0 = "01") else '0';
s_req_p1(1) <= req_i(1) when(s_pri1 = "01") else '0';
s_req_p1(2) <= req_i(2) when(s_pri2 = "01") else '0';
s_req_p1(3) <= req_i(3) when(s_pri3 = "01") else '0';
s_req_p1(4) <= req_i(4) when(s_pri4 = "01") else '0';
s_req_p1(5) <= req_i(5) when(s_pri5 = "01") else '0';
s_req_p1(6) <= req_i(6) when(s_pri6 = "01") else '0';
s_req_p1(7) <= req_i(7) when(s_pri7 = "01") else '0';
s_req_p2(0) <= req_i(0) when(s_pri0 = "10") else '0';
s_req_p2(1) <= req_i(1) when(s_pri1 = "10") else '0';
s_req_p2(2) <= req_i(2) when(s_pri2 = "10") else '0';
s_req_p2(3) <= req_i(3) when(s_pri3 = "10") else '0';
s_req_p2(4) <= req_i(4) when(s_pri4 = "10") else '0';
s_req_p2(5) <= req_i(5) when(s_pri5 = "10") else '0';
s_req_p2(6) <= req_i(6) when(s_pri6 = "10") else '0';
s_req_p2(7) <= req_i(7) when(s_pri7 = "10") else '0';
s_req_p3(0) <= req_i(0) when(s_pri0 = "11") else '0';
s_req_p3(1) <= req_i(1) when(s_pri1 = "11") else '0';
s_req_p3(2) <= req_i(2) when(s_pri2 = "11") else '0';
s_req_p3(3) <= req_i(3) when(s_pri3 = "11") else '0';
s_req_p3(4) <= req_i(4) when(s_pri4 = "11") else '0';
s_req_p3(5) <= req_i(5) when(s_pri5 = "11") else '0';
s_req_p3(6) <= req_i(6) when(s_pri6 = "11") else '0';
s_req_p3(7) <= req_i(7) when(s_pri7 = "11") else '0';
ARB0: wb_conmax_arb
port map(
clk_i => clk_i,
rst_i => rst_i,
req_i => s_req_p0,
gnt_o => s_gnt_p0,
next_i => '0'
);
ARB1: wb_conmax_arb
port map(
clk_i => clk_i,
rst_i => rst_i,
req_i => s_req_p1,
gnt_o => s_gnt_p1,
next_i => '0'
);
ARB2: wb_conmax_arb
port map(
clk_i => clk_i,
rst_i => rst_i,
req_i => s_req_p2,
gnt_o => s_gnt_p2,
next_i => '0'
);
ARB3: wb_conmax_arb
port map(
clk_i => clk_i,
rst_i => rst_i,
req_i => s_req_p3,
gnt_o => s_gnt_p3,
next_i => '0'
);
-----------------------------------------------
--Final Master Select
s_sel1 <= s_gnt_p1 when( s_pri_out(0)='1' ) else
s_gnt_p0;
s_sel2 <= s_gnt_p0 when( s_pri_out="00" ) else
s_gnt_p1 when( s_pri_out="01" ) else
s_gnt_p2 when( s_pri_out="10" ) else
s_gnt_p3;
G4: if(g_pri_sel=0) generate
sel <= s_gnt_p0;
end generate;
G5: if(g_pri_sel=1) generate
sel <= s_sel1;
end generate;
G6: if(g_pri_sel/=0 and g_pri_sel/=1) generate
sel <= s_sel2;
end generate;
end behavioral;
modules/wrc_core/wb_conmax/wb_conmax_pri_dec.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_pri_dec.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Simple Master's priority encoder
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
-- (eg. <if..generate> instead of pri_out_d0 and pri_out_d1)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_conmax_pri_dec is
generic(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel : integer := 0
);
port(
valid_i : in std_logic;
pri_i : in std_logic_vector(1 downto 0);
pri_o : out std_logic_vector(3 downto 0)
);
end wb_conmax_pri_dec;
architecture behaviour of wb_conmax_pri_dec is
signal pri_out_d0 : std_logic_vector(3 downto 0);
signal pri_out_d1 : std_logic_vector(3 downto 0);
begin
--4 priority levels
process(valid_i,pri_i)
begin
if( valid_i='0' ) then
pri_out_d1 <= "0001";
elsif( pri_i="00" ) then
pri_out_d1 <= "0001";
elsif( pri_i="01" ) then
pri_out_d1 <= "0010";
elsif( pri_i="10" ) then
pri_out_d1 <= "0100";
else
pri_out_d1 <= "1000";
end if;
end process;
--2 priority levels
process(valid_i, pri_i)
begin
if( valid_i='0' ) then
pri_out_d0 <= "0001";
elsif( pri_i="00" ) then
pri_out_d0 <= "0001";
else
pri_out_d0 <= "0010";
end if;
end process;
--select how many pririty levels
G1: if(g_pri_sel=0) generate
pri_o <= "0000";
end generate;
G2: if(g_pri_sel=1) generate
pri_o <= pri_out_d0;
end generate;
G3: if(g_pri_sel/=0 and g_pri_sel/=1) generate
pri_o <= pri_out_d1;
end generate;
end behaviour;
modules/wrc_core/wb_conmax/wb_conmax_pri_enc.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_pri_enc.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- The set of priority encoders for all Master interfaces.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_conmax_pri_enc is
generic(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel : integer := 0
);
port(
valid_i : in std_logic_vector(7 downto 0);
pri0_i : in std_logic_vector(1 downto 0);
pri1_i : in std_logic_vector(1 downto 0);
pri2_i : in std_logic_vector(1 downto 0);
pri3_i : in std_logic_vector(1 downto 0);
pri4_i : in std_logic_vector(1 downto 0);
pri5_i : in std_logic_vector(1 downto 0);
pri6_i : in std_logic_vector(1 downto 0);
pri7_i : in std_logic_vector(1 downto 0);
pri_o : out std_logic_vector(1 downto 0)
);
end wb_conmax_pri_enc;
architecture behaviour of wb_conmax_pri_enc is
component wb_conmax_pri_dec is
generic(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel : integer := 0
);
port(
valid_i : in std_logic;
pri_i : in std_logic_vector(1 downto 0);
pri_o : out std_logic_vector(3 downto 0)
);
end component;
signal s_pri0_o : std_logic_vector(3 downto 0);
signal s_pri1_o : std_logic_vector(3 downto 0);
signal s_pri2_o : std_logic_vector(3 downto 0);
signal s_pri3_o : std_logic_vector(3 downto 0);
signal s_pri4_o : std_logic_vector(3 downto 0);
signal s_pri5_o : std_logic_vector(3 downto 0);
signal s_pri6_o : std_logic_vector(3 downto 0);
signal s_pri7_o : std_logic_vector(3 downto 0);
signal s_pritmp_o : std_logic_vector(3 downto 0);
signal s_pri_out0 : std_logic_vector(1 downto 0);
signal s_pri_out1 : std_logic_vector(1 downto 0);
begin
PD0: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(0),
pri_i => pri0_i,
pri_o => s_pri0_o
);
PD1: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(1),
pri_i => pri1_i,
pri_o => s_pri1_o
);
PD2: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(2),
pri_i => pri2_i,
pri_o => s_pri2_o
);
PD3: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(3),
pri_i => pri3_i,
pri_o => s_pri3_o
);
PD4: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(4),
pri_i => pri4_i,
pri_o => s_pri4_o
);
PD5: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(5),
pri_i => pri5_i,
pri_o => s_pri5_o
);
PD6: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(6),
pri_i => pri6_i,
pri_o => s_pri6_o
);
PD7: wb_conmax_pri_dec
generic map(
g_pri_sel => g_pri_sel
)
port map(
valid_i => valid_i(7),
pri_i => pri7_i,
pri_o => s_pri7_o
);
s_pritmp_o <= s_pri0_o or s_pri1_o or s_pri2_o or s_pri3_o or s_pri4_o or
s_pri5_o or s_pri6_o or s_pri7_o;
--4 priority levels
s_pri_out1 <= "11" when ( s_pritmp_o(3)='1' ) else
"10" when ( s_pritmp_o(2)='1' ) else
"01" when ( s_pritmp_o(1)='1' ) else
"00";
--2 priority levels
s_pri_out0 <= "01" when ( s_pritmp_o(1)='1' ) else
"00";
G1: if (g_pri_sel=0) generate
pri_o <= "00";
end generate;
G2: if (g_pri_sel=1) generate
pri_o <= s_pri_out0;
end generate;
G3: if (g_pri_sel/=0 and g_pri_sel/=1) generate
pri_o <= s_pri_out1;
end generate;
end behaviour;
modules/wrc_core/wb_conmax/wb_conmax_rf.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_rf.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Register File - consists of 16 registers. Each stores configuration for
-- different Slave.
-- Each of those 16 registers is the Slave's personal priority register,
-- where the priorities for each Master are stored. The Register File is
-- accessible from Master through Slave 15th interface.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wbconmax_pkg.all;
entity wb_conmax_rf is
generic(
g_rf_addr : integer range 0 to 15 := 15 --0xF
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
--Internal WB interface
int_wb_i : in t_wb_i;
int_wb_o : out t_wb_o;
--External WB interface
ext_wb_i : in t_wb_o;
ext_wb_o : out t_wb_i;
--Configuration regs
conf_o : out t_rf_conf
);
end wb_conmax_rf;
architecture behaviour of wb_conmax_rf is
signal s_rf_sel : std_logic;
signal s_rf_dout : std_logic_vector(15 downto 0);
signal s_rf_ack : std_logic;
signal s_rf_we : std_logic;
signal s_conf : t_rf_conf;
signal s_rf_addr : std_logic_vector(3 downto 0);
begin
--Register File select logic
s_rf_addr <= std_logic_vector(to_unsigned(g_rf_addr, 4));
s_rf_sel <= int_wb_i.cyc and int_wb_i.stb when(int_wb_i.addr(c_aw-5 downto c_aw-8) = s_rf_addr )
else '0';
--Register File logic
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
s_rf_we <= s_rf_sel and int_wb_i.we and not(s_rf_we);
s_rf_ack <= s_rf_sel and not(s_rf_ack);
end if;
end process;
--Write logic
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
if(rst_i = '1') then
s_conf <= (others=> (others=>'0'));
elsif(s_rf_we='1') then
if (int_wb_i.addr(5 downto 2)=x"0") then s_conf(0) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"1") then s_conf(1) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"2") then s_conf(2) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"3") then s_conf(3) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"4") then s_conf(4) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"5") then s_conf(5) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"6") then s_conf(6) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"7") then s_conf(7) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"8") then s_conf(8) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"9") then s_conf(9) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"a") then s_conf(10) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"b") then s_conf(11) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"c") then s_conf(12) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"d") then s_conf(13) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"e") then s_conf(14) <= int_wb_i.data(15 downto 0);
elsif(int_wb_i.addr(5 downto 2)=x"f") then s_conf(15) <= int_wb_i.data(15 downto 0);
end if;
end if;
end if;
end process;
--Read logic
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
if(s_rf_sel='0') then
s_rf_dout <= x"0000";
else
if ( int_wb_i.addr(5 downto 2)=x"0" ) then s_rf_dout <= s_conf(0);
elsif( int_wb_i.addr(5 downto 2)=x"1" ) then s_rf_dout <= s_conf(1);
elsif( int_wb_i.addr(5 downto 2)=x"2" ) then s_rf_dout <= s_conf(2);
elsif( int_wb_i.addr(5 downto 2)=x"3" ) then s_rf_dout <= s_conf(3);
elsif( int_wb_i.addr(5 downto 2)=x"4" ) then s_rf_dout <= s_conf(4);
elsif( int_wb_i.addr(5 downto 2)=x"5" ) then s_rf_dout <= s_conf(5);
elsif( int_wb_i.addr(5 downto 2)=x"6" ) then s_rf_dout <= s_conf(6);
elsif( int_wb_i.addr(5 downto 2)=x"7" ) then s_rf_dout <= s_conf(7);
elsif( int_wb_i.addr(5 downto 2)=x"8" ) then s_rf_dout <= s_conf(8);
elsif( int_wb_i.addr(5 downto 2)=x"9" ) then s_rf_dout <= s_conf(9);
elsif( int_wb_i.addr(5 downto 2)=x"A" ) then s_rf_dout <= s_conf(10);
elsif( int_wb_i.addr(5 downto 2)=x"B" ) then s_rf_dout <= s_conf(11);
elsif( int_wb_i.addr(5 downto 2)=x"C" ) then s_rf_dout <= s_conf(12);
elsif( int_wb_i.addr(5 downto 2)=x"D" ) then s_rf_dout <= s_conf(13);
elsif( int_wb_i.addr(5 downto 2)=x"E" ) then s_rf_dout <= s_conf(14);
elsif( int_wb_i.addr(5 downto 2)=x"F" ) then s_rf_dout <= s_conf(15);
end if;
end if;
end if;
end process;
--Register File bypass logic
ext_wb_o.addr <= int_wb_i.addr;
ext_wb_o.sel <= int_wb_i.sel;
ext_wb_o.data <= int_wb_i.data;
ext_wb_o.cyc <= int_wb_i.cyc when(s_rf_sel='0') else '0';
ext_wb_o.stb <= int_wb_i.stb;
ext_wb_o.we <= int_wb_i.we;
int_wb_o.data <= ( (c_dw-1 downto 16 => '0') & s_rf_dout ) when(s_rf_sel='1')
else ext_wb_i.data;
int_wb_o.ack <= s_rf_ack when(s_rf_sel='1') else ext_wb_i.ack;
int_wb_o.err <= '0' when(s_rf_sel='1') else ext_wb_i.err;
int_wb_o.rty <= '0' when(s_rf_sel='1') else ext_wb_i.rty;
conf_o <= s_conf;
end behaviour;
modules/wrc_core/wb_conmax/wb_conmax_slave_if.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_slave_if.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Full interface for a single Wishbone Slave. Consists of WB Master interface,
-- Prioritizing Arbiter and multiplexer for selecting appropriate Master.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wbconmax_pkg.all;
entity wb_conmax_slave_if is
generic(
g_pri_sel : integer := 2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
conf_i : in std_logic_vector(15 downto 0);
--Slave interface
wb_slave_i : in t_wb_o;
wb_slave_o : out t_wb_i;
--Master (0 to 7) interfaces
wb_masters_i : in t_conmax_masters_i;
wb_masters_o : out t_conmax_masters_o
);
end wb_conmax_slave_if;
architecture bahaviour of wb_conmax_slave_if is
component wb_conmax_arb is
port(
clk_i : in std_logic;
rst_i : in std_logic;
req_i : in std_logic_vector(7 downto 0);
gnt_o : out std_logic_vector(2 downto 0);
next_i : in std_logic
);
end component;
component wb_conmax_msel is
generic(
g_pri_sel : integer := 0
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
conf_i : in std_logic_vector(15 downto 0);
req_i : in std_logic_vector(7 downto 0);
next_i : in std_logic;
sel : out std_logic_vector(2 downto 0)
);
end component;
signal s_wb_cyc_o : std_logic;
signal s_msel_simple, s_msel_pe, s_msel : std_logic_vector(2 downto 0);
signal s_next : std_logic;
signal s_mcyc : std_logic_vector(7 downto 0);
signal s_arb_req_i : std_logic_vector(7 downto 0);
begin
wb_slave_o.cyc <= s_wb_cyc_o;
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
s_next <= not(s_wb_cyc_o);
end if;
end process;
s_arb_req_i <= wb_masters_i(7).cyc & wb_masters_i(6).cyc & wb_masters_i(5).cyc &
wb_masters_i(4).cyc & wb_masters_i(3).cyc & wb_masters_i(2).cyc &
wb_masters_i(1).cyc & wb_masters_i(0).cyc;
--Prioritizing Arbiter
ARB: wb_conmax_arb
port map(
clk_i => clk_i,
rst_i => rst_i,
req_i => s_arb_req_i,
gnt_o => s_msel_simple,
next_i=> '0' --no round robin
);
MSEL: wb_conmax_msel
generic map(
g_pri_sel => g_pri_sel
)
port map(
clk_i => clk_i,
rst_i => rst_i,
conf_i => conf_i,
req_i => s_arb_req_i,
next_i => s_next,
sel => s_msel_pe
);
G1: if(g_pri_sel=0) generate
s_msel <= s_msel_simple;
end generate;
G2: if(g_pri_sel/=0) generate
s_msel <= s_msel_pe;
end generate;
-------------------------------------
--Address & Data Pass
wb_slave_o.addr <= wb_masters_i(0).addr when(s_msel="000") else
wb_masters_i(1).addr when(s_msel="001") else
wb_masters_i(2).addr when(s_msel="010") else
wb_masters_i(3).addr when(s_msel="011") else
wb_masters_i(4).addr when(s_msel="100") else
wb_masters_i(5).addr when(s_msel="101") else
wb_masters_i(6).addr when(s_msel="110") else
wb_masters_i(7).addr when(s_msel="111") else
(others=>'0');
wb_slave_o.sel <= wb_masters_i(0).sel when(s_msel="000") else
wb_masters_i(1).sel when(s_msel="001") else
wb_masters_i(2).sel when(s_msel="010") else
wb_masters_i(3).sel when(s_msel="011") else
wb_masters_i(4).sel when(s_msel="100") else
wb_masters_i(5).sel when(s_msel="101") else
wb_masters_i(6).sel when(s_msel="110") else
wb_masters_i(7).sel when(s_msel="111") else
(others=>'0');
wb_slave_o.data <= wb_masters_i(0).data when(s_msel="000") else
wb_masters_i(1).data when(s_msel="001") else
wb_masters_i(2).data when(s_msel="010") else
wb_masters_i(3).data when(s_msel="011") else
wb_masters_i(4).data when(s_msel="100") else
wb_masters_i(5).data when(s_msel="101") else
wb_masters_i(6).data when(s_msel="110") else
wb_masters_i(7).data when(s_msel="111") else
(others=>'0');
G_OUT: for I in 0 to 7 generate
wb_masters_o(I).data <= wb_slave_i.data;
wb_masters_o(I).ack <= wb_slave_i.ack when(s_msel= std_logic_vector(
to_unsigned(I, 3)) ) else '0';
wb_masters_o(I).err <= wb_slave_i.err when(s_msel= std_logic_vector(
to_unsigned(I, 3)) ) else '0';
wb_masters_o(I).rty <= wb_slave_i.rty when(s_msel= std_logic_vector(
to_unsigned(I, 3)) ) else '0';
end generate;
------------------------------------
--Control Signal Pass
wb_slave_o.we <= wb_masters_i(0).we when(s_msel="000") else
wb_masters_i(1).we when(s_msel="001") else
wb_masters_i(2).we when(s_msel="010") else
wb_masters_i(3).we when(s_msel="011") else
wb_masters_i(4).we when(s_msel="100") else
wb_masters_i(5).we when(s_msel="101") else
wb_masters_i(6).we when(s_msel="110") else
wb_masters_i(7).we when(s_msel="111") else
'0';
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
s_mcyc(7 downto 0) <= wb_masters_i(7).cyc & wb_masters_i(6).cyc &
wb_masters_i(5).cyc & wb_masters_i(4).cyc & wb_masters_i(3).cyc &
wb_masters_i(2).cyc & wb_masters_i(1).cyc & wb_masters_i(0).cyc;
end if;
end process;
s_wb_cyc_o <= wb_masters_i(0).cyc and s_mcyc(0) when(s_msel="000") else
wb_masters_i(1).cyc and s_mcyc(1) when(s_msel="001") else
wb_masters_i(2).cyc and s_mcyc(2) when(s_msel="010") else
wb_masters_i(3).cyc and s_mcyc(3) when(s_msel="011") else
wb_masters_i(4).cyc and s_mcyc(4) when(s_msel="100") else
wb_masters_i(5).cyc and s_mcyc(5) when(s_msel="101") else
wb_masters_i(6).cyc and s_mcyc(6) when(s_msel="110") else
wb_masters_i(7).cyc and s_mcyc(7) when(s_msel="111") else
'0';
wb_slave_o.stb <= wb_masters_i(0).stb when(s_msel="000") else
wb_masters_i(1).stb when(s_msel="001") else
wb_masters_i(2).stb when(s_msel="010") else
wb_masters_i(3).stb when(s_msel="011") else
wb_masters_i(4).stb when(s_msel="100") else
wb_masters_i(5).stb when(s_msel="101") else
wb_masters_i(6).stb when(s_msel="110") else
wb_masters_i(7).stb when(s_msel="111") else
'0';
end bahaviour;
modules/wrc_core/wb_conmax/wb_conmax_top.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_top.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wishbone Interconnect Matrix, up to 8 Masters and 16 Slaves. Features
-- prioritized arbiter inside each Slave Interface (1, 2 of 4 priority levels).
-- Allows the parallel communication between masters and slaves on
-- different interfaces.
-- It is the WISHBONE Conmax IP Core from opencores.org rewritten in VHDL (from
-- Verilog) with some code optimalization.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wbconmax_pkg.all;
entity wb_conmax_top is
generic(
g_rf_addr : integer range 0 to 15 := 15 --0xf
);
port(
clk_i : std_logic;
rst_i : std_logic;
wb_masters_i : in t_conmax_masters_i;
wb_masters_o : out t_conmax_masters_o;
wb_slaves_i : in t_conmax_slaves_i;
wb_slaves_o : out t_conmax_slaves_o
);
end wb_conmax_top;
architecture struct of wb_conmax_top is
component wb_conmax_master_if is
port(
clk_i : in std_logic;
rst_i : in std_logic;
--Master interface
wb_master_i : in t_wb_i;
wb_master_o : out t_wb_o;
--Slaves(0 to 15) interface
wb_slaves_i : in t_conmax_slaves_i;
wb_slaves_o : out t_conmax_slaves_o
);
end component;
component wb_conmax_slave_if is
generic(
g_pri_sel : integer := 2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
conf_i : in std_logic_vector(15 downto 0);
--Slave interface
wb_slave_i : in t_wb_o;
wb_slave_o : out t_wb_i;
--Master (0 to 7) interfaces
wb_masters_i : in t_conmax_masters_i;
wb_masters_o : out t_conmax_masters_o
);
end component;
component wb_conmax_rf is
generic(
g_rf_addr : integer range 0 to 15 := 15 --0xF
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
--Internal WB interface
int_wb_i : in t_wb_i;
int_wb_o : out t_wb_o;
--External WB interface
ext_wb_i : in t_wb_o;
ext_wb_o : out t_wb_i;
--Configuration regs
conf_o : out t_rf_conf
);
end component;
signal intwb_s15_i : t_wb_o;
signal intwb_s15_o : t_wb_i;
--M0Sx
signal m0_slaves_i : t_conmax_slaves_i;
signal m0_slaves_o : t_conmax_slaves_o;
signal m1_slaves_i : t_conmax_slaves_i;
signal m1_slaves_o : t_conmax_slaves_o;
signal m2_slaves_i : t_conmax_slaves_i;
signal m2_slaves_o : t_conmax_slaves_o;
signal m3_slaves_i : t_conmax_slaves_i;
signal m3_slaves_o : t_conmax_slaves_o;
signal m4_slaves_i : t_conmax_slaves_i;
signal m4_slaves_o : t_conmax_slaves_o;
signal m5_slaves_i : t_conmax_slaves_i;
signal m5_slaves_o : t_conmax_slaves_o;
signal m6_slaves_i : t_conmax_slaves_i;
signal m6_slaves_o : t_conmax_slaves_o;
signal m7_slaves_i : t_conmax_slaves_i;
signal m7_slaves_o : t_conmax_slaves_o;
signal s_conf : t_rf_conf;
signal s15_wb_masters_i : t_conmax_masters_i;
signal s15_wb_masters_o : t_conmax_masters_o;
begin
--Master interfaces
M0: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
--Master interface
wb_master_i => wb_masters_i(0),
wb_master_o => wb_masters_o(0),
--Slaves(0 to 15) interface
wb_slaves_i => m0_slaves_i,
wb_slaves_o => m0_slaves_o
);
M1: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
wb_master_i => wb_masters_i(1),
wb_master_o => wb_masters_o(1),
wb_slaves_i => m1_slaves_i,
wb_slaves_o => m1_slaves_o
);
M2: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
wb_master_i => wb_masters_i(2),
wb_master_o => wb_masters_o(2),
wb_slaves_i => m2_slaves_i,
wb_slaves_o => m2_slaves_o
);
M3: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
wb_master_i => wb_masters_i(3),
wb_master_o => wb_masters_o(3),
wb_slaves_i => m3_slaves_i,
wb_slaves_o => m3_slaves_o
);
M4: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
wb_master_i => wb_masters_i(4),
wb_master_o => wb_masters_o(4),
wb_slaves_i => m4_slaves_i,
wb_slaves_o => m4_slaves_o
);
M5: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
wb_master_i => wb_masters_i(5),
wb_master_o => wb_masters_o(5),
wb_slaves_i => m5_slaves_i,
wb_slaves_o => m5_slaves_o
);
M6: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
wb_master_i => wb_masters_i(6),
wb_master_o => wb_masters_o(6),
wb_slaves_i => m6_slaves_i,
wb_slaves_o => m6_slaves_o
);
M7: wb_conmax_master_if
port map(
clk_i => clk_i,
rst_i => rst_i,
wb_master_i => wb_masters_i(7),
wb_master_o => wb_masters_o(7),
wb_slaves_i => m7_slaves_i,
wb_slaves_o => m7_slaves_o
);
--------------------------------------------------
--Slave interfaces
S_GEN: for I in 0 to 14 generate
SLV: wb_conmax_slave_if
generic map(
g_pri_sel => g_pri_sel(I)
)
port map(
clk_i => clk_i,
rst_i => rst_i,
conf_i => s_conf(I),
--Slave interface
wb_slave_i => wb_slaves_i(I),
wb_slave_o => wb_slaves_o(I),
--Interfaces to masters
wb_masters_i(0) => m0_slaves_o(I),
wb_masters_i(1) => m1_slaves_o(I),
wb_masters_i(2) => m2_slaves_o(I),
wb_masters_i(3) => m3_slaves_o(I),
wb_masters_i(4) => m4_slaves_o(I),
wb_masters_i(5) => m5_slaves_o(I),
wb_masters_i(6) => m6_slaves_o(I),
wb_masters_i(7) => m7_slaves_o(I),
wb_masters_o(0) => m0_slaves_i(I),
wb_masters_o(1) => m1_slaves_i(I),
wb_masters_o(2) => m2_slaves_i(I),
wb_masters_o(3) => m3_slaves_i(I),
wb_masters_o(4) => m4_slaves_i(I),
wb_masters_o(5) => m5_slaves_i(I),
wb_masters_o(6) => m6_slaves_i(I),
wb_masters_o(7) => m7_slaves_i(I)
);
end generate;
s15_wb_masters_i(0) <= m0_slaves_o(15);
s15_wb_masters_i(1) <= m1_slaves_o(15);
s15_wb_masters_i(2) <= m2_slaves_o(15);
s15_wb_masters_i(3) <= m3_slaves_o(15);
s15_wb_masters_i(4) <= m4_slaves_o(15);
s15_wb_masters_i(5) <= m5_slaves_o(15);
s15_wb_masters_i(6) <= m6_slaves_o(15);
s15_wb_masters_i(7) <= m7_slaves_o(15);
m0_slaves_i(15) <= s15_wb_masters_o(0);
m1_slaves_i(15) <= s15_wb_masters_o(1);
m2_slaves_i(15) <= s15_wb_masters_o(2);
m3_slaves_i(15) <= s15_wb_masters_o(3);
m4_slaves_i(15) <= s15_wb_masters_o(4);
m5_slaves_i(15) <= s15_wb_masters_o(5);
m6_slaves_i(15) <= s15_wb_masters_o(6);
m7_slaves_i(15) <= s15_wb_masters_o(7);
SLV15: wb_conmax_slave_if
generic map(
g_pri_sel => g_pri_sel(15)
)
port map(
clk_i => clk_i,
rst_i => rst_i,
conf_i => s_conf(15),
--Slave interface
wb_slave_i => intwb_s15_i,
wb_slave_o => intwb_s15_o,
--Interfaces to masters
wb_masters_i => s15_wb_masters_i,
wb_masters_o => s15_wb_masters_o
);
---------------------------------------
--Register File
RF: wb_conmax_rf
generic map(
g_rf_addr => g_rf_addr
)
port map(
clk_i => clk_i,
rst_i => rst_i,
int_wb_i => intwb_s15_o,
int_wb_o => intwb_s15_i,
ext_wb_i => wb_slaves_i(15),
ext_wb_o => wb_slaves_o(15),
conf_o => s_conf
);
end struct;
modules/wrc_core/wb_conmax/wbconmax_pkg.vhd deleted 100644 → 0
View file @ 3d699c4f
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wbconmax_pkg.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-16
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Package for WB interconnect matrix. Defines basic constants and types used
-- to simplify WB interface connections.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package wbconmax_pkg is
type t_rf_conf is array(0 to 15) of std_logic_vector(15 downto 0);
constant c_dw : integer := 32; --data width
constant c_aw : integer := 18; --address width = max 14b (for dpram) + 4b
--for wb_intercom (Mst selects Slave)
constant c_sw : integer := 4; -- c_dw/8
--g_pri_selx := 0 (1 priority level), 1 (2 pri levels) or 2 (4 pri levels).
type t_pri_sels is array(0 to 15) of integer range 0 to 3;
constant g_pri_sel : t_pri_sels := (2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
--as in original WB conmax spec and implementation, those are
--inputs fed by WB Master from outside
type t_wb_i is record
data : std_logic_vector(c_dw-1 downto 0);
addr : std_logic_vector(c_aw-1 downto 0);
sel : std_logic_vector(c_sw-1 downto 0);
we : std_logic;
cyc : std_logic;
stb : std_logic;
end record;
type t_wb_o is record
data : std_logic_vector(c_dw-1 downto 0);
ack : std_logic;
err : std_logic;
rty : std_logic;
end record;
type t_conmax_masters_i is array(0 to 7) of t_wb_i;
type t_conmax_masters_o is array(0 to 7) of t_wb_o;
type t_conmax_slaves_i is array(0 to 15) of t_wb_o;
type t_conmax_slaves_o is array(0 to 15) of t_wb_i;
end wbconmax_pkg;
modules/wrc_core/wr_core.vhd
View file @ 7b5a7685
This diff is collapsed.
modules/wrc_core/wrc_periph.vhd
View file @ 7b5a7685
This diff is collapsed.
modules/wrc_core/wrc_syscon_pkg.vhd 0 → 100644
View file @ 7b5a7685
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Core System Controller
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Nov 30 15:12:21 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sysc_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_sysc_in_registers is record
gpsr_fmc_scl_i : std_logic;
gpsr_fmc_sda_i : std_logic;
gpsr_btn1_i : std_logic;
gpsr_btn2_i : std_logic;
hwfr_memsize_i : std_logic_vector(3 downto 0);
tcr_tdiv_i : std_logic_vector(11 downto 0);
tvr_i : std_logic_vector(31 downto 0);
end record;
constant c_sysc_in_registers_init_value: t_sysc_in_registers := (
gpsr_fmc_scl_i => '0',
gpsr_fmc_sda_i => '0',
gpsr_btn1_i => '0',
gpsr_btn2_i => '0',
hwfr_memsize_i => (others => '0'),
tcr_tdiv_i => (others => '0'),
tvr_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_sysc_out_registers is record
rstr_trig_o : std_logic_vector(27 downto 0);
rstr_trig_wr_o : std_logic;
rstr_rst_o : std_logic;
gpsr_led_stat_o : std_logic;
gpsr_led_link_o : std_logic;
gpsr_fmc_scl_o : std_logic;
gpsr_fmc_scl_load_o : std_logic;
gpsr_fmc_sda_o : std_logic;
gpsr_fmc_sda_load_o : std_logic;
gpsr_net_rst_o : std_logic;
gpcr_led_stat_o : std_logic;
gpcr_led_link_o : std_logic;
gpcr_fmc_scl_o : std_logic;
gpcr_fmc_sda_o : std_logic;
tcr_enable_o : std_logic;
end record;
constant c_sysc_out_registers_init_value: t_sysc_out_registers := (
rstr_trig_o => (others => '0'),
rstr_trig_wr_o => '0',
rstr_rst_o => '0',
gpsr_led_stat_o => '0',
gpsr_led_link_o => '0',
gpsr_fmc_scl_o => '0',
gpsr_fmc_scl_load_o => '0',
gpsr_fmc_sda_o => '0',
gpsr_fmc_sda_load_o => '0',
gpsr_net_rst_o => '0',
gpcr_led_stat_o => '0',
gpcr_led_link_o => '0',
gpcr_fmc_scl_o => '0',
gpcr_fmc_sda_o => '0',
tcr_enable_o => '0'
);
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
end package;
package body sysc_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers is
variable tmp: t_sysc_in_registers;
begin
tmp.gpsr_fmc_scl_i := left.gpsr_fmc_scl_i or right.gpsr_fmc_scl_i;
tmp.gpsr_fmc_sda_i := left.gpsr_fmc_sda_i or right.gpsr_fmc_sda_i;
tmp.gpsr_btn1_i := left.gpsr_btn1_i or right.gpsr_btn1_i;
tmp.gpsr_btn2_i := left.gpsr_btn2_i or right.gpsr_btn2_i;
tmp.hwfr_memsize_i := left.hwfr_memsize_i or right.hwfr_memsize_i;
tmp.tcr_tdiv_i := left.tcr_tdiv_i or right.tcr_tdiv_i;
tmp.tvr_i := left.tvr_i or right.tvr_i;
return tmp;
end function;
end package body;
modules/wrc_core/wrc_syscon_regs.h 0 → 100644
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/*
Register definitions for slave core: WR Core System Controller
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Wed Nov 30 15:45:28 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
#define __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Syscon reset register */
/* definitions for field: Reset trigger in reg: Syscon reset register */
#define SYSC_RSTR_TRIG_MASK WBGEN2_GEN_MASK(0, 28)
#define SYSC_RSTR_TRIG_SHIFT 0
#define SYSC_RSTR_TRIG_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define SYSC_RSTR_TRIG_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Reset line state value in reg: Syscon reset register */
#define SYSC_RSTR_RST WBGEN2_GEN_MASK(28, 1)
/* definitions for register: GPIO Set/Readback Register */
/* definitions for field: Status LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_LED_STAT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Link LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_LED_LINK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_FMC_SCL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_FMC_SDA WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Network AP reset in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_NET_RST WBGEN2_GEN_MASK(4, 1)
/* definitions for field: SPEC Pushbutton 1 state in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_BTN1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: SPEC Pushbutton 2 state in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_BTN2 WBGEN2_GEN_MASK(6, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
#define SYSC_GPCR_LED_STAT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Link LED in reg: GPIO Clear Register */
#define SYSC_GPCR_LED_LINK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_FMC_SCL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_FMC_SDA WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
#define SYSC_HWFR_MEMSIZE_MASK WBGEN2_GEN_MASK(0, 4)
#define SYSC_HWFR_MEMSIZE_SHIFT 0
#define SYSC_HWFR_MEMSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define SYSC_HWFR_MEMSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for register: Timer Control Register */
/* definitions for field: Timer Divider in reg: Timer Control Register */
#define SYSC_TCR_TDIV_MASK WBGEN2_GEN_MASK(0, 12)
#define SYSC_TCR_TDIV_SHIFT 0
#define SYSC_TCR_TDIV_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define SYSC_TCR_TDIV_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Timer Enable in reg: Timer Control Register */
#define SYSC_TCR_ENABLE WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Timer Counter Value Register */
/* [0x0]: REG Syscon reset register */
#define SYSC_REG_RSTR 0x00000000
/* [0x4]: REG GPIO Set/Readback Register */
#define SYSC_REG_GPSR 0x00000004
/* [0x8]: REG GPIO Clear Register */
#define SYSC_REG_GPCR 0x00000008
/* [0xc]: REG Hardware Feature Register */
#define SYSC_REG_HWFR 0x0000000c
/* [0x10]: REG Timer Control Register */
#define SYSC_REG_TCR 0x00000010
/* [0x14]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x00000014
#endif
modules/wrc_core/wrc_syscon_wb.vhd 0 → 100644
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modules/wrc_core/wrc_syscon_wb.wb
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......@@ -12,10 +12,19 @@ peripheral {
field {
name = "Reset trigger";
prefix = "HRST";
description = "Write 0xdeadbeef to reset the WR Core";
prefix = "TRIG";
description = "Write 0xdeadbee latch the state of RSTR.RST to the reset line of the LM32 CPU.";
type = PASS_THROUGH;
size = 32;
size = 28;
};
field {
name = "Reset line state value";
prefix = "RST";
description = "State of the reset line";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......@@ -148,6 +157,7 @@ peripheral {
<b>f_tick = f_clk_sys / (TDIV * 256)</b>";
prefix = "TDIV";
size = 12;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -179,4 +189,4 @@ peripheral {
};
};
\ No newline at end of file
};
modules/wrc_core/wrcore_pkg.vhd
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modules/wrc_core/xwr_core.vhd 0 → 100644
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modules/wrc_core/xwr_syscon_wb.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : WhiteRabbit Syscon
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : xwr_syscon_wb.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-11-07
-- Last update: 2011-11-07
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wrapper for wrc_syscon_wb. Uses types instead of std_logic signals and
-- can use pipelined or classic wishbone.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-11-07 1.0 greg.d Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
entity xwr_syscon_wb is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end xwr_syscon_wb;
architecture syn of xwr_syscon_wb is
component wrc_syscon_wb
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end component;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => slave_i.adr,
sl_dat_i => slave_i.dat,
sl_sel_i => slave_i.sel,
sl_cyc_i => slave_i.cyc,
sl_stb_i => slave_i.stb,
sl_we_i => slave_i.we,
sl_dat_o => slave_o.dat,
sl_ack_o => slave_o.ack,
sl_stall_o => slave_o.stall);
WRAPPED_SYSCON: wrc_syscon_wb
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(2 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
regs_i => regs_i,
regs_o => regs_o);
wb_in.adr(c_wishbone_address_width-1 downto 3) <= (others=>'0');
end syn;
syn/spec_1_1/wr_core_demo/spec_top_wrc.xise 0 → 100644
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testbench/wbp_mux/wave.do
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testbench/wrc_core/main_tb/main.sv
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testbench/wrc_core/main_tb/sw/minic.c
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......@@ -8,7 +8,7 @@
#include "endpoint_regs.h"
#define BASE_MINIC 0x10000
#define BASE_EP 0x20000
#define BASE_EP 0x10100
#define MINIC_DMA_TX_BUF_SIZE 1024
......
testbench/wrc_core/main_tb/sw/uart.c
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testbench/wrc_core/main_tb/wave.do
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top/spec_1_1/wr_core_demo/spec_top.vhd
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