- 14 May, 2019 6 commits
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Tomasz Wlostowski authored
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Maciej Lipinski authored
Provide the rate of the WR Reference Clock based on the information about the width of the PCS word. It is assumed to be related: * 16bit word with 62.5MHz clock * 8bit word with 125MHz clock
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Maciej Lipinski authored
WR Streamers need to be used with WR Reference clock of 62.5MHz, adding generic to specify what ref_clk is used (125MHz by default, or 62.5MHz)
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Maciej Lipinski authored
The generic g_ref_clk_rate was dummy, i.e. never used. The module pulse_stamper is used with input reference clock (and tm_cycles_i) of 125MHz and 62.5MHz clock, in the wr_streamers. Added possibility to define what clock is used (default 125MHz or 62.5MHz). In any case, the output timestamp is of cycle period of 8ns.
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Maciej Lipinski authored
This follows update of the top in: top/spec_1_1/wr_streamers_demo that is used by this testbench. After the updated of the top, few changes were needed in the simulation: - update of inputs/outputs in the main - addition of a (dummy) synthesis_description.vhd (this is generated when synthesising, yet needed for compilation in simulation. Since, the data in this file is not really important in simulation, no need for generation of the file, dummy version is OK - waveform updated
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Maciej Lipinski authored
The streamers demo was using very old top. With the updated of resets, etc, it stopped working (at least the testbench did stop). So, I finally updated this top to work (in the testbench at least) with the new BSP. This required a major re-do of the top. I left from the old as much as I could. The new top is based on the spec_ref_design. This was tested only for simulation (testbech/wr_streamers/streamers-on-spec_trigger-distribution). A commit with updates to simulation follows.
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- 09 May, 2019 1 commit
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Grzegorz Daniluk authored
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- 30 Apr, 2019 1 commit
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Dimitris Lampridis authored
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- 26 Apr, 2019 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 23 Apr, 2019 6 commits
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Dimitris Lampridis authored
hdl: introduce "g_verbose" generic to control the printing of information messages during simulation. This affects in particular the messages about loading of LM32 software, as well as the messages printed by the wishbone crossbar, listing all attached slaves. If omitted, the default value is "TRUE", in order to maintain backward compatibility.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
GTP reference clock is connected to CLK01 and/or CLK11 in our instance of GTP_DUAL. According to UG386, figure 2-3, page 41, REFSELDYPLLx must be set to '4' to select CLK10/CLK11. This is done in order to ensure backward compatibility with previous versions of the Xilinx platform support package.
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- 11 Mar, 2019 10 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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- 08 Mar, 2019 1 commit
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Tomasz Wlostowski authored
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- 06 Mar, 2019 13 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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