Signed-off-by: Adam Wujek <adam.wujek@cern.ch>

Compiled from wrpc-sw:
1c028e8e Merge branch 'minic_fifo' into proposed_master

This also removes Xilinx ISE synthesis warnings like:
wr-cores\platform\xilinx\wr_gtp_phy\wr_gtp_phy_spartan6.vhd" Line 246: <bufio2>
remains a black-box since it has no binding entity.

Adam Wujek authored 8 years ago and Grzegorz Daniluk committed 8 years ago

Signed-off-by: Adam Wujek <adam.wujek@cern.ch>

This constraint is needed only when DMTD samples 125m refclock (clock has to be
fed to D input of a flip-flop). However, in case of SPEC we use
g_divide_input_by_2 generic in the dmtd_with_deglitcher. This re-generates
62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D input of a
flip-flop.
This constraint would be needed e.g. for Kintex, where refclock is 62.5MHz and
we don't use g_divide_input_by_2.