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Commit fd86db70 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'spec-demo_cleanup' into proposed_master

parents b85cbb60 f985aa7c
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platform/xilinx/wr_xilinx_pkg.vhd
+ 55
− 5
View file @ fd86db70
......@@ -30,6 +30,15 @@ package wr_xilinx_pkg is
dpll_data : std_logic_vector(15 downto 0);
end record;
type t_extref_to_wrc is record
clk_10m_ref : std_logic;
clk_125m_ref : std_logic;
locked : std_logic;
stopped : std_logic;
pps : std_logic;
end record;
-- types for 8-bit Serdes
type t_phy_8bits_to_wrc is record
ref_clk : std_logic;
tx_disparity : std_logic;
......@@ -55,12 +64,47 @@ package wr_xilinx_pkg is
sfp_tx_disable : std_logic;
end record;
constant c_dummy_phy8_from_wrc : t_phy_8bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
-- types for 16-bit Serdes
type t_phy_16bits_to_wrc is record
ref_clk : std_logic;
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0);
rx_clk : std_logic;
rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
rdy : std_logic;
sfp_tx_fault : std_logic;
sfp_los : std_logic;
end record;
type t_phy_16bits_from_wrc is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0);
loopen_vec : std_logic_vector(2 downto 0);
tx_prbs_sel : std_logic_vector(2 downto 0);
sfp_tx_disable : std_logic;
end record;
constant c_dummy_phy16_from_wrc : t_phy_16bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
-------------------------------------------------------------------------------------------
component xwrc_platform_xilinx
generic
(
g_simulation : integer := 0;
g_family : string := "spartan6"
g_family : string := "spartan6";
g_with_10m_refin : integer := 0
);
port (
local_reset_n_i : in std_logic;
......@@ -69,9 +113,11 @@ package wr_xilinx_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic; -- 125 MHz GTP reference
clk_10m_ref_p_i : in std_logic := '0'; -- 10MHz external reference
clk_10m_ref_n_i : in std_logic := '0'; -- 10MHz external reference
pps_ext_i : in std_logic := '0'; -- external 1-PPS from reference
dac_sclk_o : out std_logic; -- Serial Clock Line
dac_din_o : out std_logic; -- Serial Data Line
dac_clr_n_o : out std_logic; -- ?
dac_cs1_n_o : out std_logic; -- Chip Select
dac_cs2_n_o : out std_logic; -- Chip Select
carrier_onewire_b : inout std_logic := '1'; -- read temperature sensor
......@@ -90,12 +136,16 @@ package wr_xilinx_pkg is
clk_125m_pllref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
dacs_i : in t_dacs_from_wrc;
phy_o : out t_phy_8bits_to_wrc;
phy_i : in t_phy_8bits_from_wrc;
phy8_o : out t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
phy16_o : out t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
owr_en_i : in std_logic_vector(1 downto 0);
owr_o : out std_logic_vector(1 downto 0);
sfp_config_o : out t_sfp_to_wrc;
sfp_config_i : in t_sfp_from_wrc
sfp_config_i : in t_sfp_from_wrc;
ext_ref_o : out t_extref_to_wrc;
ext_ref_rst_i : in std_logic := '0'
);
end component;
......
platform/xilinx/xwrc_platform_xilinx.vhd
+ 88
− 26
View file @ fd86db70
......@@ -3,7 +3,7 @@
-- Project : WR PTP Core
-------------------------------------------------------------------------------
-- File : wrc_platform_xilinx.vhd
-- Author : Maciej Lipinski
-- Author : Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN
-- Platform : FPGA-generic
-- Standard : VHDL'93
......@@ -48,6 +48,7 @@ use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wrcore_pkg.all;
use work.gencores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -58,7 +59,8 @@ entity xwrc_platform_xilinx is
-- setting g_simulation to TRUE will speed up some initialization processes
g_simulation : integer := 0;
-- define the Familiy of Xilinx FPGAs (supported: now only spartan6)
g_family : string := "spartan6"
g_family : string := "spartan6";
g_with_10m_refin : integer := 0
);
port (
local_reset_n_i : in std_logic;
......@@ -71,12 +73,18 @@ entity xwrc_platform_xilinx is
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic; -- 125 MHz GTP reference
---------------------------------------------------------------------------------------
-- External 10MHz & 1-PPS reference
---------------------------------------------------------------------------------------
clk_10m_ref_p_i : in std_logic := '0'; -- 10MHz external reference
clk_10m_ref_n_i : in std_logic := '0'; -- 10MHz external reference
pps_ext_i : in std_logic := '0'; -- external 1-PPS from reference
---------------------------------------------------------------------------------------
-- I2C to control DAC
---------------------------------------------------------------------------------------
dac_sclk_o : out std_logic; -- Serial Clock Line
dac_din_o : out std_logic; -- Serial Data Line
dac_clr_n_o : out std_logic; -- ?
dac_cs1_n_o : out std_logic; -- Chip Select
dac_cs2_n_o : out std_logic; -- Chip Select
......@@ -108,12 +116,16 @@ entity xwrc_platform_xilinx is
clk_125m_pllref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
dacs_i : in t_dacs_from_wrc;
phy_o : out t_phy_8bits_to_wrc;
phy_i : in t_phy_8bits_from_wrc;
phy8_o : out t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
phy16_o : out t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
owr_en_i : in std_logic_vector(1 downto 0);
owr_o : out std_logic_vector(1 downto 0);
sfp_config_o : out t_sfp_to_wrc;
sfp_config_i : in t_sfp_from_wrc
sfp_config_i : in t_sfp_from_wrc;
ext_ref_o : out t_extref_to_wrc;
ext_ref_rst_i : in std_logic := '0'
);
end xwrc_platform_xilinx;
......@@ -130,10 +142,16 @@ architecture rtl of xwrc_platform_xilinx is
signal clk_62m5_pllout_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_pllref_bufg : std_logic;
signal clk_125m_gtp : std_logic;
signal clk_62m5_sys : std_logic;
signal clk_80m_ADC : std_logic;
-- External 10MHz reference
signal clk_10m_ref : std_logic;
signal clk_10m_ref_bufg : std_logic;
signal ext_pll_rst : std_logic;
-- WRPC <--> EEPROM on FMC
signal wrc_scl_out : std_logic;
signal wrc_sda_out : std_logic;
......@@ -181,7 +199,7 @@ begin
LOCKED => open,
RST => '0',
CLKFBIN => clk_62m5_pllout_fb_pllref,
CLKIN => clk_125m_pllref);
CLKIN => clk_125m_pllref_bufg);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
......@@ -244,8 +262,13 @@ begin
-- to top-level port)
IB => clk_125m_pllref_n_i );-- Diff_n buffer input (connect directly
-- to top-level port)
phy_o.ref_clk <= clk_125m_pllref;
clk_125m_pllref_o <= clk_125m_pllref;
cmp_pllrefclk_bufg : BUFG
port map (
O => clk_125m_pllref_bufg,
I => clk_125m_pllref);
phy8_o.ref_clk <= clk_125m_pllref_bufg;
clk_125m_pllref_o <= clk_125m_pllref_bufg;
-------------------------------------------------------------------------------------------
-- Dedicated clock for GTP --ML: different in SPEC -> need check
......@@ -261,6 +284,43 @@ begin
IB => clk_125m_gtp_n_i
);
-------------------------------------------------------------------------------------------
-- PLL for multiplying external 10MHz reference clock
-------------------------------------------------------------------------------------------
GEN_EXT_REF: if g_with_10m_refin = 1 generate
U_Ext_BUF : IBUFGDS
generic map (
DIFF_TERM => true)
port map (
O => clk_10m_ref,
I => clk_10m_ref_p_i,
IB => clk_10m_ref_n_i);
U_Ext_BUFG : BUFG
port map (
O => clk_10m_ref_bufg,
I => clk_10m_ref);
U_Ext_PLL : ext_pll_10_to_125m
port map (
clk_ext_i => clk_10m_ref_bufg,
clk_ext_mul_o => ext_ref_o.clk_125m_ref,
rst_a_i => ext_pll_rst,
clk_in_stopped_o => ext_ref_o.stopped,
locked_o => ext_ref_o.locked);
U_Extend_EXT_Reset : gc_extend_pulse
generic map (
g_width => 1000)
port map (
clk_i => clk_62m5_sys,
rst_n_i => local_reset_n_i,
pulse_i => ext_ref_rst_i,
extended_o => ext_pll_rst);
end generate;
ext_ref_o.clk_10m_ref <= clk_10m_ref_bufg;
ext_ref_o.pps <= pps_ext_i;
-------------------------------------------------------------------------------
-- Tri-state access to devices (SFP, one wire thermometer)
-------------------------------------------------------------------------------
......@@ -287,7 +347,7 @@ begin
g_enable_ch1 => 1)
port map (
gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_ref_clk_i => clk_125m_pllref_bufg,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
......@@ -299,21 +359,21 @@ begin
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_i.tx_data,
ch1_tx_k_i => phy_i.tx_k(0),
ch1_tx_disparity_o => phy_o.tx_disparity,
ch1_tx_enc_err_o => phy_o.tx_enc_err,
ch1_rx_data_o => phy_o.rx_data,
ch1_rx_rbclk_o => phy_o.rx_clk,
ch1_rx_k_o => phy_o.rx_k(0),
ch1_rx_enc_err_o => phy_o.rx_enc_err,
ch1_rx_bitslide_o => phy_o.rx_bitslide,
ch1_rst_i => phy_i.rst,
ch1_loopen_i => phy_i.loopen,
ch1_loopen_vec_i => phy_i.loopen_vec,
ch1_tx_prbs_sel_i => phy_i.tx_prbs_sel,
ch1_rdy_o => phy_o.rdy,
ch1_ref_clk_i => clk_125m_pllref_bufg,
ch1_tx_data_i => phy8_i.tx_data,
ch1_tx_k_i => phy8_i.tx_k(0),
ch1_tx_disparity_o => phy8_o.tx_disparity,
ch1_tx_enc_err_o => phy8_o.tx_enc_err,
ch1_rx_data_o => phy8_o.rx_data,
ch1_rx_rbclk_o => phy8_o.rx_clk,
ch1_rx_k_o => phy8_o.rx_k(0),
ch1_rx_enc_err_o => phy8_o.rx_enc_err,
ch1_rx_bitslide_o => phy8_o.rx_bitslide,
ch1_rst_i => phy8_i.rst,
ch1_loopen_i => phy8_i.loopen,
ch1_loopen_vec_i => phy8_i.loopen_vec,
ch1_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
ch1_rdy_o => phy8_o.rdy,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
......@@ -323,7 +383,9 @@ begin
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i
);
sfp_tx_disable_o <= '0';
sfp_tx_disable_o <= phy8_i.sfp_tx_disable;
phy8_o.sfp_tx_fault <= sfp_tx_fault_i;
phy8_o.sfp_los <= sfp_los_i;
end generate gen_phy_spartan6;
gen_phy_unknown: if(g_family /= "spartan6") generate
......
top/spec_1_1/wr_core_demo/spec_top.ucf
+ 40
− 343
View file @ fd86db70
......@@ -4,49 +4,30 @@ NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "fpga_pll_ref_clk_101_n_i" LOC = D11;
NET "fpga_pll_ref_clk_101_n_i" IOSTANDARD = "LVDS_25";
NET "fpga_pll_ref_clk_101_p_i" LOC = C11;
NET "fpga_pll_ref_clk_101_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
NET "thermo_id" LOC = D4;
NET "thermo_id" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "PRSNT_M2C_L" LOC = A2;
#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_i" LOC = G15;
NET "SFP_MOD_DEF0_i" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
......@@ -68,11 +49,6 @@ NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
NET "sfp_txn_o" LOC= A16;
#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
NET "FPGA_SCL_B" LOC = F7;
NET "FPGA_SCL_B" IOSTANDARD = "LVCMOS25";
NET "FPGA_SDA_B" LOC = F8;
......@@ -92,10 +68,11 @@ NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS25";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_N" LOC = F16;
#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
......@@ -115,30 +92,20 @@ NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
......@@ -228,282 +195,20 @@ NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
#NET "LA00_N" LOC = AB11;
#NET "LA00_N" IOSTANDARD = "LVCMOS25";
#NET "LA00_P" LOC = Y11;
#NET "LA00_P" IOSTANDARD = "LVCMOS25";
#NET "LA01_N" LOC = AB12;
#NET "LA01_N" IOSTANDARD = "LVCMOS25";
#NET "LA01_P" LOC = AA12;
#NET "LA01_P" IOSTANDARD = "LVCMOS25";
#NET "sda1_b" LOC = Y6;
#NET "sda1_b" IOSTANDARD = "LVCMOS25";
#NET "scl1_b" LOC = W6;
#NET "scl1_b" IOSTANDARD = "LVCMOS25";
#NET "LA02_N" LOC = Y6;
#NET "LA02_N" IOSTANDARD = "LVCMOS25";
#NET "LA02_P" LOC = W6;
#NET "LA02_P" IOSTANDARD = "LVCMOS25";
#NET "LA03_N" LOC = W8;
#NET "LA03_N" IOSTANDARD = "LVCMOS25";
#NET "LA03_P" LOC = V7;
##NET "LA03_P" IOSTANDARD = "LVCMOS25";
#NET "LA04_N" LOC = U8;
#NET "LA04_N" IOSTANDARD = "LVCMOS25";
#NET "LA04_P" LOC = T8;
#NET "LA04_P" IOSTANDARD = "LVCMOS25";
#NET "LA05_N" LOC = AB6;
#NET "LA05_N" IOSTANDARD = "LVCMOS25";
#NET "LA05_P" LOC = AA6;
#NET "LA05_P" IOSTANDARD = "LVCMOS25";
#NET "LA06_N" LOC = AB5;
#NET "LA06_N" IOSTANDARD = "LVCMOS25";
#NET "LA06_P" LOC = Y5;
#NET "LA06_P" IOSTANDARD = "LVCMOS25";
#NET "LA07_N" LOC = V9;
#NET "LA07_N" IOSTANDARD = "LVCMOS25";
#NET "LA07_P" LOC = U9;
#NET "LA07_P" IOSTANDARD = "LVCMOS25";
#NET "LA08_N" LOC = R8;
#NET "LA08_N" IOSTANDARD = "LVCMOS25";
#NET "LA08_P" LOC = R9;
#NET "LA08_P" IOSTANDARD = "LVCMOS25";
#NET "LA09_N" LOC = AB7;
#NET "LA09_N" IOSTANDARD = "LVCMOS25";
#NET "LA09_P" LOC = Y7;
#NET "LA09_P" IOSTANDARD = "LVCMOS25";
#NET "LA10_N" LOC = AB8;
#NET "LA10_N" IOSTANDARD = "LVCMOS25";
#NET "LA10_P" LOC = AA8;
#NET "LA10_P" IOSTANDARD = "LVCMOS25";
#NET "LA11_N" LOC = Y10;
#NET "LA11_N" IOSTANDARD = "LVCMOS25";
#NET "LA11_P" LOC = W10;
#NET "LA11_P" IOSTANDARD = "LVCMOS25";
#NET "LA12_N" LOC = U10;
#NET "LA12_N" IOSTANDARD = "LVCMOS25";
#NET "LA12_P" LOC = T10;
#NET "LA12_P" IOSTANDARD = "LVCMOS25";
#NET "LA13_N" LOC = AB9;
#NET "LA13_N" IOSTANDARD = "LVCMOS25";
#NET "LA13_P" LOC = Y9;
#NET "LA13_P" IOSTANDARD = "LVCMOS25";
#NET "LA14_N" LOC = AB4;
#NET "LA14_N" IOSTANDARD = "LVCMOS25";
#NET "LA14_P" LOC = AA4;
#NET "LA14_P" IOSTANDARD = "LVCMOS25";
#NET "LA15_N" LOC = W11;
#NET "LA15_N" IOSTANDARD = "LVCMOS25";
#NET "LA15_P" LOC = V11;
#NET "LA15_P" IOSTANDARD = "LVCMOS25";
#NET "LA16_N" LOC = AB15;
#NET "LA16_N" IOSTANDARD = "LVCMOS25";
#NET "LA16_P" LOC = Y15;
#NET "LA16_P" IOSTANDARD = "LVCMOS25";
#NET "LA17_N" LOC = AB13;
#NET "LA17_N" IOSTANDARD = "LVCMOS25";
#NET "LA17_P" LOC = Y13;
#NET "LA17_P" IOSTANDARD = "LVCMOS25";
#NET "LA18_N" LOC = U12;
#NET "LA18_N" IOSTANDARD = "LVCMOS25";
#NET "LA18_P" LOC = T12;
#NET "LA18_P" IOSTANDARD = "LVCMOS25";
#NET "LA19_N" LOC = Y12;
#NET "LA19_N" IOSTANDARD = "LVCMOS25";
#NET "LA19_P" LOC = W12;
#NET "LA19_P" IOSTANDARD = "LVCMOS25";
#NET "LA20_N" LOC = T11;
#NET "LA20_N" IOSTANDARD = "LVCMOS25";
#NET "LA20_P" LOC = R11;
#NET "LA20_P" IOSTANDARD = "LVCMOS25";
#NET "LA21_N" LOC = W13;
#NET "LA21_N" IOSTANDARD = "LVCMOS25";
#NET "LA21_P" LOC = V13;
#NET "LA21_P" IOSTANDARD = "LVCMOS25";
#NET "LA22_N" LOC = T14;
#NET "LA22_N" IOSTANDARD = "LVCMOS25";
#NET "LA22_P" LOC = R13;
#NET "LA22_P" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" LOC = AB16;
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "LA24_N" LOC = Y14;
#NET "LA24_N" IOSTANDARD = "LVCMOS25";
#NET "LA24_P" LOC = W14;
#NET "LA24_P" IOSTANDARD = "LVCMOS25";
#NET "LA25_N" LOC = U15;
#NET "LA25_N" IOSTANDARD = "LVCMOS25";
#NET "LA25_P" LOC = T15;
#NET "LA25_P" IOSTANDARD = "LVCMOS25";
#NET "LA26_N" LOC = AB17;
#NET "LA26_N" IOSTANDARD = "LVCMOS25";
#NET "LA26_P" LOC = Y17;
#NET "LA26_P" IOSTANDARD = "LVCMOS25";
#NET "LA27_N" LOC = AB18;
#NET "LA27_N" IOSTANDARD = "LVCMOS25";
#NET "LA27_P" LOC = AA18;
#NET "LA27_P" IOSTANDARD = "LVCMOS25";
#NET "LA28_N" LOC = W15;
#NET "LA28_N" IOSTANDARD = "LVCMOS25";
#NET "LA28_P" LOC = Y16;
#NET "LA28_P" IOSTANDARD = "LVCMOS25";
#NET "LA29_N" LOC = Y18;
#NET "LA29_N" IOSTANDARD = "LVCMOS25";
#NET "LA29_P" LOC = W17;
#NET "LA29_P" IOSTANDARD = "LVCMOS25";
#NET "LA30_N" LOC = W18;
#NET "LA30_N" IOSTANDARD = "LVCMOS25";
#NET "LA30_P" LOC = V17;
#NET "LA30_P" IOSTANDARD = "LVCMOS25";
#NET "LA31_N" LOC = C18;
#NET "LA31_N" IOSTANDARD = "LVCMOS25";
#NET "LA31_P" LOC = D17;
#NET "LA31_P" IOSTANDARD = "LVCMOS25";
#NET "LA32_N" LOC = A20;
#NET "LA32_N" IOSTANDARD = "LVCMOS25";
#NET "LA32_P" LOC = B20;
#NET "LA32_P" IOSTANDARD = "LVCMOS25";
#NET "LA33_N" LOC = A19;
#NET "LA33_N" IOSTANDARD = "LVCMOS25";
#NET "LA33_P" LOC = C19;
#NET "LA33_P" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SCL" LOC = AA14;
#NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SDA" LOC = AB14;
#NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";#NET "DDR3_CAS_N" LOC = M4;
#NET "DDR3_CAS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CK_N" LOC = K3;
#NET "DDR3_CK_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CK_P" LOC = K4;
#NET "DDR3_CK_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CKE" LOC = F2;
#NET "DDR3_CKE" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDM" LOC = N4;
#NET "DDR3_LDM" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDQS_N" LOC = N1;
#NET "DDR3_LDQS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDQS_P" LOC = N3;
#NET "DDR3_LDQS_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_ODT" LOC = L6;
#NET "DDR3_ODT" IOSTANDARD = "LVCMOS15";
#NET "DDR3_RAS_N" LOC = M5;
#NET "DDR3_RAS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_RESET_N" LOC = E3;
#NET "DDR3_RESET_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDM" LOC = P3;
#NET "DDR3_UDM" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDQS_N" LOC = V1;
#NET "DDR3_UDQS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDQS_P" LOC = V2;
#NET "DDR3_UDQS_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_WE_N" LOC = H2;
#NET "DDR3_WE_N" IOSTANDARD = "LVCMOS15";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
#NET "PCB_VER[0]" LOC = P5;
#NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[1]" LOC = P4;
#NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[2]" LOC = AA2;
#NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[3]" LOC = AA1;
#NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[4]" LOC = N6;
#NET "PCB_VER[4]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[5]" LOC = N7;
#NET "PCB_VER[5]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[6]" LOC = U4;
#NET "PCB_VER[6]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[7]" LOC = T4;
#NET "PCB_VER[7]" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A0" LOC = K2;
#NET "DDR3_A0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A1" LOC = K1;
#NET "DDR3_A1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A2" LOC = K5;
#NET "DDR3_A2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A3" LOC = M6;
#NET "DDR3_A3" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A4" LOC = H3;
#NET "DDR3_A4" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A5" LOC = M3;
#NET "DDR3_A5" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A6" LOC = L4;
#NET "DDR3_A6" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A7" LOC = K6;
#NET "DDR3_A7" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A8" LOC = G3;
#NET "DDR3_A8" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A9" LOC = G1;
#NET "DDR3_A9" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A10" LOC = J4;
#NET "DDR3_A10" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A11" LOC = E1;
#NET "DDR3_A11" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A12" LOC = F1;
#NET "DDR3_A12" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A13" LOC = J6;
#NET "DDR3_A13" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A14" LOC = H5;
#NET "DDR3_A14" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA0" LOC = J3;
#NET "DDR3_BA0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA1" LOC = J1;
#NET "DDR3_BA1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA2" LOC = H1;
#NET "DDR3_BA2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ0" LOC = R3;
#NET "DDR3_DQ0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ1" LOC = R1;
#NET "DDR3_DQ1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ2" LOC = P2;
#NET "DDR3_DQ2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ3" LOC = P1;
#NET "DDR3_DQ3" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ4" LOC = L3;
#NET "DDR3_DQ4" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ5" LOC = L1;
#NET "DDR3_DQ5" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ6" LOC = M2;
#NET "DDR3_DQ6" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ7" LOC = M1;
#NET "DDR3_DQ7" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ8" LOC = T2;
#NET "DDR3_DQ8" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ9" LOC = T1;
#NET "DDR3_DQ9" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ10" LOC = U3;
#NET "DDR3_DQ10" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ11" LOC = U1;
#NET "DDR3_DQ11" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ12" LOC = W3;
#NET "DDR3_DQ12" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ13" LOC = W1;
#NET "DDR3_DQ13" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ14" LOC = Y2;
#NET "DDR3_DQ14" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ15" LOC = Y1;
#NET "DDR3_DQ15" IOSTANDARD = "LVCMOS15";
NET "L_CLKp" TNM_NET = "l_clkp_grp";
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
########################################################
## Pin definitions for FmcDio5chttl + SPEC v1.1/2.0 ##
########################################################
......@@ -513,7 +218,6 @@ NET "dio_n_o[4]" LOC= U8;
NET "dio_p_o[4]" IOSTANDARD=LVDS_25;
NET "dio_n_o[4]" IOSTANDARD=LVDS_25;
NET "dio_p_o[3]" LOC= U9;
NET "dio_n_o[3]" LOC= V9;
NET "dio_p_o[3]" IOSTANDARD=LVDS_25;
......@@ -534,12 +238,6 @@ NET "dio_n_o[0]" LOC= Y18;
NET "dio_p_o[0]" IOSTANDARD=LVDS_25;
NET "dio_n_o[0]" IOSTANDARD=LVDS_25;
NET "dio_sdn_n_o" LOC= V11;
NET "dio_sdn_n_o" IOSTANDARD=LVCMOS25;
NET "dio_sdn_ck_n_o" LOC= Y5;
NET "dio_sdn_ck_n_o" IOSTANDARD=LVCMOS25;
# DIO output enable/termination enable
NET "dio_oe_n_o[4]" LOC= AA6;
NET "dio_oe_n_o[3]" LOC= W10;
......@@ -565,9 +263,6 @@ NET "dio_term_en_o[2]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[1]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[0]" IOSTANDARD=LVCMOS25;
NET "dio_onewire_b" LOC=AB16;
NET "dio_onewire_b" IOSTANDARD=LVCMOS25;
# DIO inputs
NET "dio_clk_p_i" LOC=L20;
NET "dio_clk_p_i" IOSTANDARD=LVDS_25;
......@@ -606,18 +301,6 @@ NET "dio_led_bot_o" LOC= AB12;
NET "dio_led_bot_o" IOSTANDARD=LVCMOS25;
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
# System clock
# DDR3
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
......@@ -630,19 +313,33 @@ NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "fpga_pll_ref_clk_101_p_i" TNM_NET = fpga_pll_ref_clk_101_p_i;
TIMESPEC TS_fpga_pll_ref_clk_101_p_i = PERIOD "fpga_pll_ref_clk_101_p_i" 8 ns HIGH 50%;
NET "fpga_pll_ref_clk_101_n_i" TNM_NET = fpga_pll_ref_clk_101_n_i;
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50%;
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
# 10MHz reference clock input
NET "dio_clk_p_i" TNM_NET = dio_clk_p_i;
TIMESPEC TS_dio_clk_p_i = PERIOD "dio_clk_p_i" 100 ns HIGH 50%;
NET "dio_clk_n_i" TNM_NET = dio_clk_n_i;
TIMESPEC TS_dio_clk_n_i = PERIOD "dio_clk_n_i" 100 ns HIGH 50%;
# Needed only when DMTD samples 125m refclock (clock has to be fed to D input of
# a flip-flop).
# However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher.
# This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D
# input of a flip-flop. This constraint would be needed e.g. for Kintex, where
# refclock is 62.5MHz and we don't use g_divide_input_by_2.
#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2016/11/14
NET "WRC_PLATFORM/gen_phy_spartan6.cmp_GTP/ch1_gtp_clkout_int<1>" TNM_NET = WRC_PLATFORM/gen_phy_spartan6.cmp_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_WRC_PLATFORM_gen_phy_spartan6_cmp_GTP_ch1_gtp_clkout_int_1_ = PERIOD "WRC_PLATFORM/gen_phy_spartan6.cmp_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
INST "U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
top/spec_1_1/wr_core_demo/spec_top.vhd
+ 400
− 498
View file @ fd86db70
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