Most files changes due to change from LM32 to URV

fasec ip - fix constraints but comment clk_gtx_tx create_generated_clock cause of critical warning ..no logical path from master clock..

Not obvious and if not done, file type is 'unknown' and not available
later on for the loader. See Xilinx support article 71226.

fasec - fix IP files path, have to be relative wrt component.xml; ignoring vivado warning that all files should be below the IP xml

Instead of generating the 62.5MHz DMTD clock using a process, divide an incoming
125MHz clock by 2 using a BUFR on 7Series FPGA (similarly to the Ultrascale+
path).

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Remove default assignments of clock signals when g_use_default_plls = FALSE
that actually originate from the phys / transceivers and are thus independant
of said generic (signals would have multiple writers / assignements).

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Remove internal component declarations, remove unused signals.
Fix names

if the user design already includes the transceiver
(this change avoid inclusion of usless/conflicting xdc files)

Add generic: Artix7 gtp depends on rx_byte_is_aligned

See merge request !11

Update family7 gtx-lp and gthe4-lp, now using lpdc via wishbone mdio

See merge request !9

wrc_core sim for wrpc-v5 works

See merge request !10

Now, in testbench/wrc_core there are two folders - modelsim and riviera. Each of them contains
Manifest.py and run.do adjusted for the simulation with ModelSim/Riviera. One should navigate to
one of these folders to run the simulation with the corresponding simulator.

The streamers-on-spec_trigger-distribution testbench works now for wrpc-v5 in ModelSim.
However, it does not work with Riviera. The problem is that the secureip library cannot be
compiled for the spartan 6 and the Riviera version after 2008.