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Update family7 gtx-lp and gthe4-lp, now using lpdc via wishbone mdio

Peter Jansweijer requested to merge peter_lpdc_via_wishbone_mdio into wrpc-v5

An update is needed for gtx-lp and gthe4-lp since control and status of the low phase drift phy's is now controlled via the wishbone bus and mdio registers.

commit 0e3962b4 adds the possibility to select a phy reference clock of 100 MHz (it defaults to 125 MHz as normally used).

The latter is going to be used in the BabyWR design. The rationale behind a 100 MHz phy reference clock is that this clock is an integer multiple of the 10 MHz WR phase aligned clock that is generated in the FPGA. This allows for reclocking the poor phase noise digital domain 10 MHz WR phase aligned clock with the (low phase noise) 100 MHz phy reference clock.

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