pxie-fmc: support aux pll

board/pxie-fmc/xwrc_board_pxie_fmc.vhd

@@ -73,6 +73,8 @@ entity xwrc_board_pxie_fmc is
     -- size the generic diag interface
     g_diag_ro_size              : integer              := 0;
     g_diag_rw_size              : integer              := 0;
+    -- User-defined PLL_BASE outputs config
+    g_aux_pll_cfg               : t_auxpll_cfg_array   := c_AUXPLL_CFG_ARRAY_DEFAULT;
     g_aux_sdb                   : t_sdb_device         := c_wrc_periph3_sdb
     );
   port (
@@ -98,6 +100,8 @@ entity xwrc_board_pxie_fmc is
     clk_sys_62m5_o      : out std_logic;
     -- 125MHz ref clock output
     clk_ref_125m_o      : out std_logic;
+    -- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
+    clk_pll_aux_o       : out std_logic_vector(3 downto 0);
     -- active low reset outputs, synchronous to 62m5 and 125m clocks
     rst_sys_62m5_n_o    : out std_logic;
     rst_ref_125m_n_o    : out std_logic;
@@ -283,6 +287,7 @@ begin  -- architecture struct
       g_fpga_family               => "zynqus",
       g_with_external_clock_input => FALSE,
       g_use_default_plls          => TRUE,
+      g_aux_pll_cfg               => g_aux_pll_cfg,
       g_simulation                => g_simulation)
     port map (
       areset_n_i            => areset_n_i,
@@ -300,6 +305,7 @@ begin  -- architecture struct
       clk_62m5_sys_o        => clk_pll_62m5,
       clk_125m_ref_o        => clk_pll_125m,
       clk_62m5_dmtd_o       => clk_pll_dmtd,
+      clk_pll_aux_o         => clk_pll_aux_o,
       pll_locked_o          => pll_locked,
       phy16_o               => phy16_to_wrc,
       phy16_i               => phy16_from_wrc);