Tomasz Wlostowski authored 1 year ago and Tristan Gingold committed 1 year ago

- we now use Cheby for the MDIO register layout (small changes in the naming)
- dropped LPC_CTRL/LPC_STAT registers in favour of a full WB master interface to the PHY.

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

Such glitch happened after the autonegotation FSM was in pseudo
AN_ENABLED state caused by synced=LOW (in this state, link_ok is
HIGH). When synced goes HIGH, the FSM enters "proper" AN_ENABLED
state, it drives link_ok LOW.s All in all, this glitch is avoided
then we use delayed synced_d1 to produce the final link_ok_o.
I did it here to avoid any changes to autonegotiation state machine.

Register stores new fields that were added to MCR since MDIO regs can be only
16-bits.

Peter Jansweijer authored 10 years ago and Grzegorz Daniluk committed 9 years ago

added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width loopback to MDIO Control register. Be careful: Single bit loopback was relocated to accomodate loopback(2:0)!

Earlier we were resetting clock alignment fifo (ep_rx_path) when GTX was still
not locked and was not producing rx clock. Xilinx document ug363 (Virtex-6 FPGA
Memory Resources) says that dual-clock fifo should have reset signal asserted
for at least three clock cycles. Chipscope says our fifo was reset while rx
clock was not yet there. This apparently was causing Xilinx fifo block going
crazy once every few boots. As a result FIFO was asserting _empty_ and
_almost_full_ outputs at the same time causing the rx path to stall forever.

Maciej Lipinski authored 11 years ago and Grzegorz Daniluk committed 11 years ago

added loads of stuff to debug (with chipcscope) endpoint in the switch - the commit potentially to remove when cleaning

Maciej Lipinski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

TRU: adding features and I/F necessary for TRU unit. I/F for packet filter, flow ctr and adding functionality for killing link

Tomasz Wlostowski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

wr_endpoint: modified VCR1 register to allow direct access to VLAN Untagged Set/Injection Template Buffer. Also, re-generated the wishbone slaves with new wbgen2

Tomasz Wlostowski authored 11 years ago and Grzegorz Daniluk committed 11 years ago

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

The modifications include:
- adding pps_valid_i line, indicating if the PPS input is not being re-adjusted (which may result in generation of incorrect timestamps)
- TX/RX timestamp incorrect flags: when 1, the client should discard the timestamp, as it may be broken.
- TXTSU interface change (to avoid confusion between former valid output and new incorrect output)
  * txtsu_valid_o -> txtsu_stb_o
  * txtsu_tsval_o -> txtsu_ts_value_o
  * new port      -> txtsu_ts_incorrect_o

wr_endpoint/ep_1000basex_pcs.vhd: de-assert busy flag when there's no link to avoid blocking packet source, added some comments