wr_endpoint: keep rx pcs and rx clk alignment fifo in reset until serdes is locked

Earlier we were resetting clock alignment fifo (ep_rx_path) when GTX was still
not locked and was not producing rx clock. Xilinx document ug363 (Virtex-6 FPGA
Memory Resources) says that dual-clock fifo should have reset signal asserted
for at least three clock cycles. Chipscope says our fifo was reset while rx
clock was not yet there. This apparently was causing Xilinx fifo block going
crazy once every few boots. As a result FIFO was asserting _empty_ and
_almost_full_ outputs at the same time causing the rx path to stall forever.