This constraint is needed only when DMTD samples 125m refclock (clock has to be
fed to D input of a flip-flop). However, in case of SPEC we use
g_divide_input_by_2 generic in the dmtd_with_deglitcher. This re-generates
62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D input of a
flip-flop.
This constraint would be needed e.g. for Kintex, where refclock is 62.5MHz and
we don't use g_divide_input_by_2.

the WR Switch so that later we can merge.