- record_full interface option: use general cores's library WB interface types
  to simplify connection of the cores. Enabled by -H record_full option
- use byte addressing for WB address (in record_full mode)
- allow specifying package name with record/component definitions (hdl_package field in the peripheral record)
- fixed indentation & formatting of produced VHDL package files
- include VHDL component declaration in the package files

vhdl: get rid of "internal signals for (foreseen) compatibility". They are not used and generate a ton of warnings

TODO: except texinfo doc output!

For now, the access from the bus is RW, we need to define a new RO/RO mode in wbgen.

target_pipelined_wb: in case of an if-generate, also add a second (complementary) if-generate to drive all outputs when the if-generate condition is false

Signed-off-by: Federico Vaga <federico.vaga@gmail.com>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

cgen_vhdl: fixed f_x_to_zero() function in generated VHDL package causing synthesis error on Mentor Precision

initial support for 'optional' parameter (conditional instantiation of RAMs and FIFOs depending on a user-defined generic value)

fixed readback value of write-only (monostable) bits to 0. See Wesley's message on white-rabbit-dev, dated 12/02/2013 for explanation

git-svn-id: http://svn.ohwr.org/wishbone-gen@27 4537843c-45c2-4d80-8546-c3283569414f

VHDL code generator: use separate records for in and out registers to avoid problems with tristate2logic in XIlinx tools

git-svn-id: http://svn.ohwr.org/wishbone-gen@26 4537843c-45c2-4d80-8546-c3283569414f

git-svn-id: http://svn.ohwr.org/wishbone-gen@25 4537843c-45c2-4d80-8546-c3283569414f

git-svn-id: http://svn.ohwr.org/wishbone-gen@24 4537843c-45c2-4d80-8546-c3283569414f

git-svn-id: http://svn.ohwr.org/wishbone-gen@23 4537843c-45c2-4d80-8546-c3283569414f